nxp: imx8ulp: switch to native Zephyr drivers and timer domain

Switch to Zephyr native drivers and timer domain. This
includes:
	1) Switching all imx8ulp topologies to timer domain.
	2) Disabling Zephyr DMA domain
	3) Various interrupt-related fixes via Kconfig-related
	ifdef logic.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

app/boards/imx8ulp_evk_mimx8ud7_adsp.conf

@@ -12,3 +12,5 @@ CONFIG_DMA_NXP_EDMA_ENABLE_HALFMAJOR_IRQ=y
 # TODO: remove this from here. Should be extracted
 # from DAI bespoke configuration or DTS.
 CONFIG_SAI_FIFO_WORD_SIZE=2
+
+CONFIG_ZEPHYR_NATIVE_DRIVERS=y

src/drivers/imx/ipc.c

@@ -33,15 +33,15 @@
 
 LOG_MODULE_REGISTER(ipc_task, CONFIG_SOF_LOG_LEVEL);
 
-#if defined(CONFIG_ARM64) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8X)
+#ifndef CONFIG_IMX8M
 /* thanks to the fact that ARM's GIC is supported
  * by Zephyr there's no need to clear interrupts
  * explicitly. This should already be done by Zephyr
  * after executing the ISR. This macro is used for
  * linkage purposes on ARM64-based platforms.
  */
 #define interrupt_clear(irq)
-#endif /* CONFIG_ARM64 */
+#endif /* CONFIG_IMX8M */
 
 /* 389c9186-5a7d-4ad1-a02c-a02ecdadfb33 */
 DECLARE_SOF_UUID("ipc-task", ipc_task_uuid, 0x389c9186, 0x5a7d, 0x4ad1,

src/platform/Kconfig

@@ -116,7 +116,6 @@ config IMX8ULP
 	select IMX
 	select IMX_EDMA
 	select IMX_INTERRUPT_GENERIC
-	select SCHEDULE_DMA_MULTI_CHANNEL
 	help
 	 Select if your target platform is imx8ulp-compatible.
 	 imx.8ulp support dsp.

src/platform/imx8ulp/include/platform/platform.h

@@ -24,7 +24,7 @@ struct timer;
 #define LPSRAM_SIZE 16384
 
 /* IPC Interrupt */
-#define PLATFORM_IPC_INTERRUPT		IRQ_NUM_MU3
+#define PLATFORM_IPC_INTERRUPT		15
 #define PLATFORM_IPC_INTERRUPT_NAME	NULL
 
 /* Host page size */

src/platform/imx8ulp/platform.c

@@ -156,11 +156,6 @@ int platform_init(struct sof *sof)
 	sof->cpu_timers = sof->platform_timer;
 #endif
 
-#ifdef __ZEPHYR__
-	/* initialize cascade interrupts before any usage */
-	interrupt_init(sof);
-#endif
-
 	platform_interrupt_init();
 	platform_clock_init(sof);
 	scheduler_init_edf();
@@ -182,15 +177,6 @@ int platform_init(struct sof *sof)
 	if (ret < 0)
 		return -ENODEV;
 
-	/* Init EDMA platform domain */
-	sof->platform_dma_domain = dma_multi_chan_domain_init
-			(&sof->dma_info->dma_array[0], 1,
-			 PLATFORM_DEFAULT_CLOCK, false);
-
-	/* i.MX platform DMA domain will be full synchronous, no time dependent */
-	sof->platform_dma_domain->full_sync = true;
-	scheduler_init_ll(sof->platform_dma_domain);
-
 	/* initialize the host IPC mechanims */
 	ipc_init(sof);
 

tools/topology/topology1/sof-imx8ulp-9x9-btsco.m4

@@ -61,14 +61,14 @@ dnl     period, priority, core, time_domain)
 DAI_ADD(sof/pipe-dai-playback.m4,
 	1, SAI, 6, sai6-bt-sco-pcm-wb,
 	PIPELINE_SOURCE_1, 2, s16le,
-	1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
+	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
 
 # capture DAI is SAI6 using 2 periods
 # Buffers use s16le format, with 16 frame per 1000us on core 0 with priority 0
 DAI_ADD(sof/pipe-dai-capture.m4,
 	2, SAI, 6, sai6-bt-sco-pcm-wb,
 	PIPELINE_SINK_2, 2, s16le,
-	1000, 0, 0)
+	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
 
 # PCM Low Latency, id 0
 

tools/topology/topology1/sof-imx8ulp-btsco.m4

@@ -62,14 +62,14 @@ dnl     period, priority, core, time_domain)
 DAI_ADD(sof/pipe-dai-playback.m4,
 	1, SAI, 5, sai5-bt-sco-pcm-wb,
 	PIPELINE_SOURCE_1, 2, s16le,
-	1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
+	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
 
 # capture DAI is SAI5 using 2 periods
 # Buffers use s16le format, with 16 frame per 1000us on core 0 with priority 0
 DAI_ADD(sof/pipe-dai-capture.m4,
 	2, SAI, 5, sai5-bt-sco-pcm-wb,
 	PIPELINE_SINK_2, 2, s16le,
-	1000, 0, 0)
+	1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
 
 # PCM Low Latency, id 0
 

zephyr/CMakeLists.txt

@@ -288,25 +288,19 @@ endif()
 
 if (CONFIG_SOC_MIMX8UD7_ADSP)
 	zephyr_library_sources(
-		${SOF_DRIVERS_PATH}/generic/dummy-dma.c
-		${SOF_DRIVERS_PATH}/imx/edma.c
-		${SOF_DRIVERS_PATH}/imx/sai.c
 		${SOF_DRIVERS_PATH}/imx/ipc.c
-		${SOF_DRIVERS_PATH}/imx/interrupt-generic.c
 	)
 
 	# Platform sources
 	zephyr_library_sources(
 		${SOF_PLATFORM_PATH}/imx8ulp/platform.c
 		${SOF_PLATFORM_PATH}/imx8ulp/lib/clk.c
-		${SOF_PLATFORM_PATH}/imx8ulp/lib/dai.c
-		${SOF_PLATFORM_PATH}/imx8ulp/lib/dma.c
 		${SOF_PLATFORM_PATH}/imx8ulp/lib/memory.c
 	)
 
 	# SOF core infrastructure - runs on top of Zephyr
 	zephyr_library_sources(
-		${SOF_SRC_PATH}/drivers/interrupt.c
+		lib/dma.c
 	)
 
 	zephyr_library_sources(${SOF_SRC_PATH}/schedule/zephyr_ll.c)

zephyr/Kconfig

@@ -30,7 +30,7 @@ config SOF_ZEPHYR_STRICT_HEADERS
 
 config DMA_DOMAIN
 	bool "Enable the usage of DMA domain."
-	default y if IMX8M || IMX8ULP
+	default y if IMX8M
 	help
 	  This enables the usage of the DMA domain in scheduling.
 

zephyr/include/rtos/interrupt.h

@@ -11,7 +11,7 @@
 /* TODO: to be removed completely when the following platforms are switched
  * to native drivers.
  */
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
+#if defined(CONFIG_IMX8M)
 /* imx currently has no IRQ driver in Zephyr so we force to xtos IRQ */
 #include "../../../xtos/include/rtos/interrupt.h"
 #else
@@ -50,7 +50,7 @@ static inline int interrupt_get_irq(unsigned int irq, const char *cascade)
 {
 #if defined(CONFIG_LIBRARY) || defined(CONFIG_ACE) || defined(CONFIG_CAVS) || \
 	defined(CONFIG_ZEPHYR_POSIX) || defined(CONFIG_ARM64) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_IMX8X)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8X) || defined(CONFIG_IMX8ULP)
 	return irq;
 #else
 	if (cascade == irq_name_level2)

zephyr/wrapper.c

@@ -55,7 +55,7 @@ const char irq_name_level2[] = "level2";
 const char irq_name_level5[] = "level5";
 
 /* imx currently has no IRQ driver in Zephyr so we force to xtos IRQ */
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
+#if defined(CONFIG_IMX8M)
 int interrupt_register(uint32_t irq, void(*handler)(void *arg), void *arg)
 {
 #ifdef CONFIG_DYNAMIC_INTERRUPTS