Skip to content

Commit

Permalink
Make trace.py use IFF1 to determine whether interrupts are enabled
Browse files Browse the repository at this point in the history
  • Loading branch information
@skoolkid
skoolkid committed Feb 9, 2024
1 parent 276648a commit be900de
Show file tree
Hide file tree
Showing 2 changed files with 20 additions and 20 deletions.
2 changes: 1 addition & 1 deletion skoolkit/trace.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -175,7 +175,7 @@ def run(snafile, options, config):
else:
memory, org = make_snapshot(snafile, options.org)[:2]
if snapshot:
state = {'im': snapshot.im, 'iff': snapshot.iff2, 'tstates': snapshot.tstates}
state = {'im': snapshot.im, 'iff': snapshot.iff1, 'tstates': snapshot.tstates}
border = snapshot.border
out7ffd = snapshot.out7ffd
outfffd = snapshot.outfffd
Expand Down
38 changes: 19 additions & 19 deletions tests/test_trace.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -406,7 +406,7 @@ def test_interrupt_mode_0(self):
stop = 0x8002
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 0, 'tstates': 69884}
registers = {'PC': start, 'iff1': 1, 'im': 0, 'tstates': 69884}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -426,7 +426,7 @@ def test_interrupt_mode_1(self):
stop = 0x8002
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69884}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69884}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -449,7 +449,7 @@ def test_interrupt_mode_2(self):
stop = 0x7ffd
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 69882}
registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 69882}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -470,7 +470,7 @@ def test_interrupt_without_halt(self):
stop = 0x8003
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69882}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69882}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -493,7 +493,7 @@ def test_interrupt_with_ei(self):
stop = 0x8004
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69882}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69882}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -517,7 +517,7 @@ def test_interrupt_with_di(self):
stop = 0x8004
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69882}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69882}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -539,7 +539,7 @@ def test_interrupt_with_dd_prefix(self):
ram = [0] * 49152
ram[0x1C00] = ram[0x1C04] = 0xFF # KSTATE0/4
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -562,7 +562,7 @@ def test_interrupt_with_fd_prefix(self):
ram = [0] * 49152
ram[0x1C00] = ram[0x1C04] = 0xFF # KSTATE0/4
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -588,7 +588,7 @@ def test_interrupt_with_ddfd_chain(self):
ram = [0] * 49152
ram[0x1C00] = ram[0x1C04] = 0xFF # KSTATE0/4
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand All @@ -612,7 +612,7 @@ def test_interrupt_at_exact_frame_boundary(self):
stop = 0x8002
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69884}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69884}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand Down Expand Up @@ -642,7 +642,7 @@ def test_interrupt_with_djnz(self):
stop = 0x7fff
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69805}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69805}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file} {outfile}')
self.assertEqual(error, '')
Expand All @@ -667,7 +667,7 @@ def test_interrupt_with_ldir(self):
stop = 0x7fff
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69805}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69805}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file} {outfile}')
self.assertEqual(error, '')
Expand All @@ -692,7 +692,7 @@ def test_interrupt_with_lddr(self):
stop = 0x7fff
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69805}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69805}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file} {outfile}')
self.assertEqual(error, '')
Expand All @@ -707,7 +707,7 @@ def test_interrupt_mode_1_with_timestamps(self):
stop = 0x8002
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69884}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69884}
z80file = self.write_z80_file(None, ram, registers=registers)
trace_line = 'TraceLine={t} ${pc:04X} {i}'
output, error = self.run_trace(('-I', trace_line, '-S', str(stop), '-v', z80file))
Expand All @@ -732,7 +732,7 @@ def test_interrupt_mode_2_with_timestamps(self):
stop = 0x7ffd
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 69884}
registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 69884}
z80file = self.write_z80_file(None, ram, registers=registers)
trace_line = 'TraceLine={t} ${pc:04X} {i}'
output, error = self.run_trace(('-I', trace_line, '-S', str(stop), '-v', z80file))
Expand All @@ -756,7 +756,7 @@ def test_interrupt_routine_executed_twice_while_int_is_active_48k(self):
stop = 0x7fff
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 69884}
registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 69884}
z80file = self.write_z80_file(None, ram, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand Down Expand Up @@ -784,7 +784,7 @@ def test_interrupt_routine_executed_twice_while_int_is_active_128k(self):
stop = 0x7fff
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'I': 127, 'iff2': 1, 'im': 2, 'tstates': 70904}
registers = {'PC': start, 'I': 127, 'iff1': 1, 'im': 2, 'tstates': 70904}
z80file = self.write_z80_file(None, ram, machine_id=4, registers=registers)
output, error = self.run_trace(f'-S {stop} -v {z80file}')
self.assertEqual(error, '')
Expand Down Expand Up @@ -928,7 +928,7 @@ def test_option_cmio(self):
stop = 0x8000
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 14335}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 14335}
z80file = self.write_z80_file(None, ram, registers=registers)
trace_line = 'TraceLine={t} ${pc:04X} {i}'
exp_output = """
Expand Down Expand Up @@ -1174,7 +1174,7 @@ def test_option_no_interrupts(self):
stop = 0x8002
ram = [0] * 49152
ram[start - 0x4000:start - 0x4000 + len(data)] = data
registers = {'PC': start, 'iff2': 1, 'im': 1, 'tstates': 69886}
registers = {'PC': start, 'iff1': 1, 'im': 1, 'tstates': 69886}
z80file = self.write_z80_file(None, ram, registers=registers)
exp_output = dedent("""
$8000 NOP
Expand Down

0 comments on commit be900de

Please sign in to comment.