code header clean up

slaclab · Jul 24, 2024 · 1d7ea48 · 1d7ea48
1 parent abfae44
commit 1d7ea48
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diff --git a/protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd b/protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPcieGpuAsyncCore.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Support for GpuDirectAsync like data transport to/from a GPU

diff --git a/protocol/pip/rtl/AxiPciePipCore.vhd b/protocol/pip/rtl/AxiPciePipCore.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePipCore.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: PCIe Intercommunication Protocol (PIP) Core
@@ -19,7 +18,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/protocol/pip/rtl/AxiPciePipReg.vhd b/protocol/pip/rtl/AxiPciePipReg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePipReg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: PCIe Intercommunication Protocol (PIP) Core
@@ -19,7 +18,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/protocol/pip/rtl/AxiPciePipRx.vhd b/protocol/pip/rtl/AxiPciePipRx.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePipRx.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: PCIe Intercommunication Protocol (PIP) Receiver Module
@@ -19,7 +18,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/protocol/pip/rtl/AxiPciePipTx.vhd b/protocol/pip/rtl/AxiPciePipTx.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePipTx.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: PCIe Intercommunication Protocol (PIP) Receiver Module
@@ -19,7 +18,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/protocol/pip/tb/AxiPciePipCoreTb.vhd b/protocol/pip/tb/AxiPciePipCoreTb.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePipCoreTb.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Simulation Testbed for testing the FPGA module
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;