updating XilinxAlveoU55c from 40b to 64b address

slaclab · Jul 24, 2024 · 533b0fa · 533b0fa
1 parent c309f14
commit 533b0fa
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Showing 6 changed files with 52 additions and 52 deletions.
diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/ip/XilinxAlveoU55cPciePhyGen3x16.dcp b/hardware/XilinxAlveoU55c/pcie-3x16/ip/XilinxAlveoU55cPciePhyGen3x16.dcp
diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/ip/XilinxAlveoU55cPciePhyGen3x16.xci b/hardware/XilinxAlveoU55c/pcie-3x16/ip/XilinxAlveoU55cPciePhyGen3x16.xci
diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cPciePhyWrapper.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cPciePhyWrapper.vhd
@@ -80,7 +80,7 @@ architecture mapping of XilinxAlveoU55cPciePhyWrapper is
          usr_irq_req     : in  std_logic_vector(0 downto 0);
          usr_irq_ack     : out std_logic_vector(0 downto 0);
          m_axib_awid     : out std_logic_vector(3 downto 0);
-         m_axib_awaddr   : out std_logic_vector(39 downto 0);
+         m_axib_awaddr   : out std_logic_vector(63 downto 0);
          m_axib_awlen    : out std_logic_vector(7 downto 0);
          m_axib_awsize   : out std_logic_vector(2 downto 0);
          m_axib_awburst  : out std_logic_vector(1 downto 0);
@@ -99,7 +99,7 @@ architecture mapping of XilinxAlveoU55cPciePhyWrapper is
          m_axib_bvalid   : in  std_logic;
          m_axib_bready   : out std_logic;
          m_axib_arid     : out std_logic_vector(3 downto 0);
-         m_axib_araddr   : out std_logic_vector(39 downto 0);
+         m_axib_araddr   : out std_logic_vector(63 downto 0);
          m_axib_arlen    : out std_logic_vector(7 downto 0);
          m_axib_arsize   : out std_logic_vector(2 downto 0);
          m_axib_arburst  : out std_logic_vector(1 downto 0);
@@ -135,7 +135,7 @@ architecture mapping of XilinxAlveoU55cPciePhyWrapper is
          s_axil_rready   : in  std_logic;
          interrupt_out   : out std_logic;
          s_axib_awid     : in  std_logic_vector(3 downto 0);
-         s_axib_awaddr   : in  std_logic_vector(39 downto 0);
+         s_axib_awaddr   : in  std_logic_vector(63 downto 0);
          s_axib_awregion : in  std_logic_vector(3 downto 0);
          s_axib_awlen    : in  std_logic_vector(7 downto 0);
          s_axib_awsize   : in  std_logic_vector(2 downto 0);
@@ -147,7 +147,7 @@ architecture mapping of XilinxAlveoU55cPciePhyWrapper is
          s_axib_wvalid   : in  std_logic;
          s_axib_bready   : in  std_logic;
          s_axib_arid     : in  std_logic_vector(3 downto 0);
-         s_axib_araddr   : in  std_logic_vector(39 downto 0);
+         s_axib_araddr   : in  std_logic_vector(63 downto 0);
          s_axib_arregion : in  std_logic_vector(3 downto 0);
          s_axib_arlen    : in  std_logic_vector(7 downto 0);
          s_axib_arsize   : in  std_logic_vector(2 downto 0);

diff --git a/hardware/XilinxAlveoU55c/pcie-4x8/ip/XilinxAlveoU55cPciePhyGen4x8.dcp b/hardware/XilinxAlveoU55c/pcie-4x8/ip/XilinxAlveoU55cPciePhyGen4x8.dcp