code header clean up

slaclab · Jul 25, 2024 · c1918e8 · c1918e8
1 parent 9feb3e1
commit c1918e8
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diff --git a/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd b/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AbacoPc821PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd b/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core

diff --git a/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd b/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core

diff --git a/hardware/AlphaDataKu3/pcie/rtl/AlphaDataKu3PciePhyWrapper.vhd b/hardware/AlphaDataKu3/pcie/rtl/AlphaDataKu3PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AlphaDataKu3PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/AlphaDataKu3/rtl/AlphaDataKu3Core.vhd b/hardware/AlphaDataKu3/rtl/AlphaDataKu3Core.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AlphaDataKu3Core.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: AXI PCIe Core for ADM-PCIE-KU3 board (PCIe GEN3 x 8 lanes)
@@ -34,7 +33,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/AlphaDataKu3/rtl/AxiPciePkg.vhd b/hardware/AlphaDataKu3/rtl/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/AlphaDataKu3/rtl/TerminateQsfp.vhd b/hardware/AlphaDataKu3/rtl/TerminateQsfp.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : TerminateQsfp.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: TerminateQsfp File
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 

diff --git a/hardware/BittWareXupVv8/core/BittWareXupVv8Core.vhd b/hardware/BittWareXupVv8/core/BittWareXupVv8Core.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : BittWareXupVv8Core.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: AXI PCIe Core for BittWare XUP-VV8 (PCIe GEN3 x 16 lanes)

diff --git a/hardware/BittWareXupVv8/core/TerminateQsfp.vhd b/hardware/BittWareXupVv8/core/TerminateQsfp.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : TerminateQsfp.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: TerminateQsfp File

diff --git a/hardware/BittWareXupVv8/core/VU13P/AxiPciePkg.vhd b/hardware/BittWareXupVv8/core/VU13P/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core

diff --git a/hardware/BittWareXupVv8/core/VU9P/AxiPciePkg.vhd b/hardware/BittWareXupVv8/core/VU9P/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core

diff --git a/hardware/BittWareXupVv8/ddr/rtl/MigAll.vhd b/hardware/BittWareXupVv8/ddr/rtl/MigAll.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigAll.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/BittWareXupVv8/pcie/rtl/BittWareXupVv8PciePhyWrapper.vhd b/hardware/BittWareXupVv8/pcie/rtl/BittWareXupVv8PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : BittWareXupVv8PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/SlacPgpCardG4/pcie/rtl/SlacPgpCardG4PciePhyWrapper.vhd b/hardware/SlacPgpCardG4/pcie/rtl/SlacPgpCardG4PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : SlacPgpCardG4PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/SlacPgpCardG4/rtl/AxiPciePkg.vhd b/hardware/SlacPgpCardG4/rtl/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Core.vhd b/hardware/SlacPgpCardG4/rtl/SlacPgpCardG4Core.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : SlacPgpCardG4Core.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: AXI PCIe Core for SLAC PGP Gen4 board (PCIe GEN3 x 8 lanes)
@@ -19,7 +18,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/XilinxAlveoU200/core/AxiPciePkg.vhd b/hardware/XilinxAlveoU200/core/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/XilinxAlveoU200/core/TerminateQsfp.vhd b/hardware/XilinxAlveoU200/core/TerminateQsfp.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : TerminateQsfp.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: TerminateQsfp File
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/XilinxAlveoU200/core/XilinxAlveoU200Core.vhd b/hardware/XilinxAlveoU200/core/XilinxAlveoU200Core.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : XilinxAlveoU200Core.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: AXI PCIe Core for Xilinx Alveo U200 board (PCIe GEN3 x 16 lanes)

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/Mig0.vhd b/hardware/XilinxAlveoU200/ddr/rtl/Mig0.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig0.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/Mig1.vhd b/hardware/XilinxAlveoU200/ddr/rtl/Mig1.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig1.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/Mig2.vhd b/hardware/XilinxAlveoU200/ddr/rtl/Mig2.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig2.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/Mig3.vhd b/hardware/XilinxAlveoU200/ddr/rtl/Mig3.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig3.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigAll.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigAll.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigAll.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigClkConvtWrapper.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigClkConvtWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigClkConvtWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description:
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/XilinxAlveoU200/ddr/rtl/MigPkg.vhd b/hardware/XilinxAlveoU200/ddr/rtl/MigPkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigPkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for MIG Core

diff --git a/hardware/XilinxAlveoU200/pcie/rtl/XilinxAlveoU200PciePhyWrapper.vhd b/hardware/XilinxAlveoU200/pcie/rtl/XilinxAlveoU200PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : XilinxAlveoU200PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/XilinxAlveoU250/core/AxiPciePkg.vhd b/hardware/XilinxAlveoU250/core/AxiPciePkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : AxiPciePkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for AXI PCIe Core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/XilinxAlveoU250/core/TerminateQsfp.vhd b/hardware/XilinxAlveoU250/core/TerminateQsfp.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : TerminateQsfp.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: TerminateQsfp File
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/XilinxAlveoU250/core/XilinxAlveoU250Core.vhd b/hardware/XilinxAlveoU250/core/XilinxAlveoU250Core.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : XilinxAlveoU250Core.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: AXI PCIe Core for Xilinx Alveo U250 board (PCIe GEN3 x 16 lanes)
@@ -19,7 +18,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiLitePkg.all;

diff --git a/hardware/XilinxAlveoU250/ddr/rtl/Mig0.vhd b/hardware/XilinxAlveoU250/ddr/rtl/Mig0.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig0.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU250/ddr/rtl/Mig1.vhd b/hardware/XilinxAlveoU250/ddr/rtl/Mig1.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig1.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU250/ddr/rtl/Mig2.vhd b/hardware/XilinxAlveoU250/ddr/rtl/Mig2.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig2.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU250/ddr/rtl/Mig3.vhd b/hardware/XilinxAlveoU250/ddr/rtl/Mig3.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig3.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU250/ddr/rtl/MigAll.vhd b/hardware/XilinxAlveoU250/ddr/rtl/MigAll.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigAll.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/XilinxAlveoU250/ddr/rtl/MigPkg.vhd b/hardware/XilinxAlveoU250/ddr/rtl/MigPkg.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigPkg.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Package file for MIG Core

diff --git a/hardware/XilinxAlveoU250/pcie/rtl/XilinxAlveoU250PciePhyWrapper.vhd b/hardware/XilinxAlveoU250/pcie/rtl/XilinxAlveoU250PciePhyWrapper.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : XilinxAlveoU250PciePhyWrapper.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for AXI PCIe Core
@@ -18,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;

diff --git a/hardware/XilinxAlveoU280/ddr/rtl/Mig0.vhd b/hardware/XilinxAlveoU280/ddr/rtl/Mig0.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig0.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU280/ddr/rtl/Mig1.vhd b/hardware/XilinxAlveoU280/ddr/rtl/Mig1.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : Mig1.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core

diff --git a/hardware/XilinxAlveoU280/ddr/rtl/MigAll.vhd b/hardware/XilinxAlveoU280/ddr/rtl/MigAll.vhd
@@ -1,5 +1,4 @@
 -------------------------------------------------------------------------------
--- File       : MigAll.vhd
 -- Company    : SLAC National Accelerator Laboratory
 -------------------------------------------------------------------------------
 -- Description: Wrapper for the MIG core
@@ -16,7 +15,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;