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Add initilization values for all tx registers
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@bengineerd
bengineerd committed Jul 21, 2023
1 parent 8284a0f commit 11daafd
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Showing 3 changed files with 87 additions and 87 deletions.
84 changes: 42 additions & 42 deletions protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -117,48 +117,48 @@ end Pgp2fcTxCell;
architecture Pgp2fcTxCell of Pgp2fcTxCell is

-- Local Signals
signal muxFrameTxValid : sl;
signal muxFrameTxSOF : sl;
signal muxFrameTxEOF : sl;
signal muxFrameTxEOFE : sl;
signal muxFrameTxData : slv(15 downto 0);
signal muxRemAlmostFull : sl;
signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0);
signal cellCntRst : sl;
signal nxtFrameTxReady : sl;
signal nxtType : slv(2 downto 0);
signal nxtTypeLast : slv(2 downto 0);
signal curTypeLast : slv(2 downto 0);
signal nxtTxSOF : sl;
signal nxtTxEOF : sl;
signal nxtTxAck : sl;
signal nxtData : slv(15 downto 0);
signal eocWord : slv(15 downto 0);
signal socWord : slv(15 downto 0);
signal crcWordA : slv(15 downto 0);
signal crcWordB : slv(15 downto 0);
signal serialCntEn : sl;
signal vc0Serial : slv(5 downto 0);
signal vc1Serial : slv(5 downto 0);
signal vc2Serial : slv(5 downto 0);
signal vc3Serial : slv(5 downto 0);
signal muxSerial : slv(5 downto 0);
signal dly0Data : slv(15 downto 0);
signal dly0Type : slv(2 downto 0);
signal dly1Data : slv(15 downto 0);
signal dly1Type : slv(2 downto 0);
signal dly2Data : slv(15 downto 0);
signal dly2Type : slv(2 downto 0);
signal dly3Data : slv(15 downto 0);
signal dly3Type : slv(2 downto 0);
signal dly4Data : slv(15 downto 0);
signal dly4Type : slv(2 downto 0);
signal int0FrameTxReady : sl;
signal int1FrameTxReady : sl;
signal int2FrameTxReady : sl;
signal int3FrameTxReady : sl;
signal intTimeout : sl;
signal intOverflow : slv(3 downto 0);
signal muxFrameTxValid : sl;
signal muxFrameTxSOF : sl;
signal muxFrameTxEOF : sl;
signal muxFrameTxEOFE : sl;
signal muxFrameTxData : slv(15 downto 0);
signal muxRemAlmostFull : sl;
signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0);
signal cellCntRst : sl;
signal nxtFrameTxReady : sl;
signal nxtType : slv(2 downto 0);
signal nxtTypeLast : slv(2 downto 0);
signal curTypeLast : slv(2 downto 0);
signal nxtTxSOF : sl;
signal nxtTxEOF : sl;
signal nxtTxAck : sl;
signal nxtData : slv(15 downto 0);
signal eocWord : slv(15 downto 0);
signal socWord : slv(15 downto 0);
signal crcWordA : slv(15 downto 0);
signal crcWordB : slv(15 downto 0);
signal serialCntEn : sl;
signal vc0Serial : slv(5 downto 0);
signal vc1Serial : slv(5 downto 0);
signal vc2Serial : slv(5 downto 0);
signal vc3Serial : slv(5 downto 0);
signal muxSerial : slv(5 downto 0);
signal dly0Data : slv(15 downto 0) := (others => '0');
signal dly0Type : slv(2 downto 0) := (others => '0');
signal dly1Data : slv(15 downto 0) := (others => '0');
signal dly1Type : slv(2 downto 0) := (others => '0');
signal dly2Data : slv(15 downto 0) := (others => '0');
signal dly2Type : slv(2 downto 0) := (others => '0');
signal dly3Data : slv(15 downto 0) := (others => '0');
signal dly3Type : slv(2 downto 0) := (others => '0');
signal dly4Data : slv(15 downto 0) := (others => '0');
signal dly4Type : slv(2 downto 0) := (others => '0');
signal int0FrameTxReady : sl := '0';
signal int1FrameTxReady : sl := '0';
signal int2FrameTxReady : sl := '0';
signal int3FrameTxReady : sl := '0';
signal intTimeout : sl := '0';
signal intOverflow : slv(3 downto 0) := (others => '0');

-- Transmit Data Marker
constant TX_DATA_C : slv(2 downto 0) := "000";
Expand Down
14 changes: 7 additions & 7 deletions protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ entity Pgp2fcTxPhy is
-- Fast control interface
fcValid : in sl; -- Latch fcWord and send it out, will cause pgpBusy to assert
fcWord : in slv(16*FC_WORDS_G-1 downto 0); -- Control word to send
fcSent : out sl; -- Asserted when a fast control word is sent out
fcSent : out sl := '0'; -- Asserted when a fast control word is sent out

-- Sideband data
pgpLocLinkReady : in sl; -- Far end side has link
Expand All @@ -74,12 +74,12 @@ end Pgp2fcTxPhy;
architecture Pgp2fcTxPhy of Pgp2fcTxPhy is

-- Local Signals
signal intTxLinkReady : sl;
signal intTxLinkReady : sl := '0';
signal nxtTxLinkReady : sl;
signal nxtTxData : slv(15 downto 0);
signal nxtTxDataK : slv(1 downto 0);
signal intTxData : slv(15 downto 0);
signal intTxDataK : slv(1 downto 0);
signal intTxData : slv(15 downto 0) := (others => '0');
signal intTxDataK : slv(1 downto 0) := (others => '0');
signal ltsAData : slv(15 downto 0);
signal ltsADataK : slv(1 downto 0);
signal ltsBData : slv(15 downto 0);
Expand All @@ -89,8 +89,8 @@ architecture Pgp2fcTxPhy of Pgp2fcTxPhy is
signal fcData : slv(15 downto 0);
signal fcDataK : slv(1 downto 0);

signal fcWordLatch : slv(16*FC_WORDS_G-1 downto 0);
signal fcWordCount : integer range 0 to FC_WORDS_G;
signal fcWordLatch : slv(16*FC_WORDS_G-1 downto 0) := (others => '0');
signal fcWordCount : integer range 0 to FC_WORDS_G := 0;

signal crcRst : sl;
signal crcEn : sl;
Expand All @@ -106,7 +106,7 @@ architecture Pgp2fcTxPhy of Pgp2fcTxPhy is
ST_CELL_C,
ST_EMPTY_C);

signal curState : fsm_states;
signal curState : fsm_states := ST_LOCK_C;
signal nxtState : fsm_states;
signal pendState : fsm_states; -- Next state if FC wasn't triggered
signal holdState : fsm_states;
Expand Down
76 changes: 38 additions & 38 deletions protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -33,40 +33,40 @@ entity Pgp2fcTxSched is
port (

-- System clock, reset & control
pgpTxClkEn : in sl := '1'; -- Master clock Enable
pgpTxClk : in sl; -- Master clock
pgpTxClkRst : in sl; -- Synchronous reset input
pgpTxClkEn : in sl := '1'; -- Master clock Enable
pgpTxClk : in sl; -- Master clock
pgpTxClkRst : in sl; -- Synchronous reset input

-- Link flush
pgpTxFlush : in sl; -- Flush the link
pgpTxFlush : in sl; -- Flush the link

-- Link is ready
pgpTxLinkReady : in sl; -- Local side has link
pgpTxLinkReady : in sl; -- Local side has link

-- Phy is busy
pgpTxBusy : in sl;
pgpTxBusy : in sl;

-- Cell Transmit Interface
schTxSOF : in sl; -- Cell contained SOF
schTxEOF : in sl; -- Cell contained EOF
schTxIdle : out sl; -- Force IDLE transmit
schTxReq : out sl; -- Cell transmit request
schTxAck : in sl; -- Cell transmit acknowledge
schTxTimeout : out sl; -- Cell transmit timeout
schTxDataVc : out slv(1 downto 0); -- Cell transmit virtual channel
schTxSOF : in sl; -- Cell contained SOF
schTxEOF : in sl; -- Cell contained EOF
schTxIdle : out sl; -- Force IDLE transmit
schTxReq : out sl; -- Cell transmit request
schTxAck : in sl; -- Cell transmit acknowledge
schTxTimeout : out sl; -- Cell transmit timeout
schTxDataVc : out slv(1 downto 0); -- Cell transmit virtual channel

-- VC Data Valid Signals
vc0FrameTxValid : in sl; -- User frame data is valid
vc1FrameTxValid : in sl; -- User frame data is valid
vc2FrameTxValid : in sl; -- User frame data is valid
vc3FrameTxValid : in sl; -- User frame data is valid
vc0FrameTxValid : in sl; -- User frame data is valid
vc1FrameTxValid : in sl; -- User frame data is valid
vc2FrameTxValid : in sl; -- User frame data is valid
vc3FrameTxValid : in sl; -- User frame data is valid

-- VC Flow Control Signals
vc0RemAlmostFull : in sl; -- Remote flow control
vc1RemAlmostFull : in sl; -- Remote flow control
vc2RemAlmostFull : in sl; -- Remote flow control
vc3RemAlmostFull : in sl -- Remote flow control
);
vc0RemAlmostFull : in sl; -- Remote flow control
vc1RemAlmostFull : in sl; -- Remote flow control
vc2RemAlmostFull : in sl; -- Remote flow control
vc3RemAlmostFull : in sl -- Remote flow control
);

end Pgp2fcTxSched;

Expand All @@ -76,22 +76,22 @@ architecture Pgp2fcTxSched of Pgp2fcTxSched is

-- Local Signals
signal currValid : sl;
signal currVc : slv(1 downto 0);
signal currVc : slv(1 downto 0) := "00";
signal nextVc : slv(1 downto 0);
signal arbVc : slv(1 downto 0);
signal arbValid : sl;
signal vcInFrame : slv(3 downto 0);
signal intTxReq : sl;
signal intTxIdle : sl;
signal vcInFrame : slv(3 downto 0) := (others => '0');
signal intTxReq : sl := '0';
signal intTxIdle : sl := '0';
signal nxtTxReq : sl;
signal nxtTxIdle : sl;
signal nxtTxTimeout : sl;
signal intTxTimeout : sl;
signal vcTimerA : slv(23 downto 0);
signal vcTimerB : slv(23 downto 0);
signal vcTimerC : slv(23 downto 0);
signal vcTimerD : slv(23 downto 0);
signal vcTimeout : slv(3 downto 0);
signal intTxTimeout : sl := '0';
signal vcTimerA : slv(23 downto 0) := (others => '0');
signal vcTimerB : slv(23 downto 0) := (others => '0');
signal vcTimerC : slv(23 downto 0) := (others => '0');
signal vcTimerD : slv(23 downto 0) := (others => '0');
signal vcTimeout : slv(3 downto 0) := (others => '0');
signal gateTxValid : slv(3 downto 0);

-- Schedular state
Expand All @@ -101,8 +101,8 @@ architecture Pgp2fcTxSched of Pgp2fcTxSched is
constant ST_GAP_A_C : slv(2 downto 0) := "100";
constant ST_GAP_B_C : slv(2 downto 0) := "101";
constant ST_GAP_C_C : slv(2 downto 0) := "110";
signal curState : slv(2 downto 0);
signal nxtState : slv(2 downto 0);
signal curState : slv(2 downto 0) := ST_ARB_C;
signal nxtState : slv(2 downto 0);

begin

Expand Down Expand Up @@ -268,25 +268,25 @@ begin
begin
case currVc is
when "00" =>
if gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1';
if gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1';
elsif gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1';
elsif gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1';
elsif gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1';
else arbVc <= "00"; arbValid <= '0'; end if;
when "01" =>
if gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1';
if gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1';
elsif gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1';
elsif gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1';
elsif gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1';
else arbVc <= "01"; arbValid <= '0'; end if;
when "10" =>
if gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1';
if gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1';
elsif gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1';
elsif gateTxvalid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1';
elsif gateTxvalid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1';
else arbVc <= "10"; arbValid <= '0'; end if;
when "11" =>
if gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1';
if gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1';
elsif gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1';
elsif gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1';
elsif gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1';
Expand Down

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