adding support to run SACI clock when asicRstL asserted in SACI_CLK_F…

…REERUN_G=false mode
slaclab · Sep 26, 2024 · 1ed83db · 1ed83db
1 parent 63d5f22
commit 1ed83db
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Showing 2 changed files with 22 additions and 8 deletions.
diff --git a/protocols/saci/rtl/AxiLiteSaciMaster.vhd b/protocols/saci/rtl/AxiLiteSaciMaster.vhd
@@ -43,6 +43,8 @@ entity AxiLiteSaciMaster is
       -- Optional SACI bus arbitration
       saciBusReq      : out sl;
       saciBusGr       : in  sl := '1';
+      -- Optional ASIC Global Reset
+      asicRstL        : in  sl := '1';
       -- AXI-Lite Register Interface
       axilClk         : in  sl;
       axilRst         : in  sl;
@@ -128,6 +130,7 @@ begin
       port map (
          sysClk   => axilClk,           -- [in]
          sysRst   => r.saciRst,         -- [in]
+         asicRstL => asicRstL,          -- [in]
          req      => r.req,             -- [in]
          ack      => ack,               -- [out]
          fail     => fail,              -- [out]
@@ -142,7 +145,7 @@ begin
          saciCmd  => saciCmd,           -- [out]
          saciRsp  => saciRsp);          -- [in]
 
-   comb : process (ack, axilReadMaster, axilRst, axilWriteMaster, fail, r, rdData, saciBusGr) is
+   comb : process (ack, asicRstL, axilReadMaster, axilRst, axilWriteMaster, fail, r, rdData, saciBusGr) is
       variable v          : RegType;
       variable axilStatus : AxiLiteStatusType;
       variable resp       : slv(1 downto 0);
@@ -170,7 +173,7 @@ begin
             v.saciRst := '0';
             v.timer   := 0;
             v.saciBusReq := '0';
-            if (saciBusGr = '1') then
+            if (saciBusGr = '1') and (asicRstL = '1') then
                -- Check for a write request
                if (axilStatus.writeEnable = '1') then
                   v.saciBusReq := '1';

diff --git a/protocols/saci/rtl/SaciMaster2.vhd b/protocols/saci/rtl/SaciMaster2.vhd
@@ -19,7 +19,6 @@ use IEEE.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 
@@ -33,9 +32,13 @@ entity SaciMaster2 is
       SACI_NUM_CHIPS_G   : positive := 1;
       SACI_RSP_BUSSED_G  : boolean  := false);
    port (
-      sysClk : in sl;                   -- Main clock
+      -- Clock and Reset
+      sysClk : in sl;
       sysRst : in sl;
 
+      -- Optional ASIC Global Reset
+      asicRstL : in  sl := '1';
+
       -- Request interface
       req    : in  sl;
       ack    : out sl;
@@ -67,6 +70,7 @@ architecture rtl of SaciMaster2 is
       state      : StateType;
       shiftReg   : slv(52 downto 0);
       shiftCount : slv(5 downto 0);
+      asicRstL   : slv(31 downto 0);
 
       --Saci clk gen
       clkCount       : slv(SACI_CLK_COUNTER_SIZE_C downto 0);
@@ -88,6 +92,7 @@ architecture rtl of SaciMaster2 is
       state          => IDLE_S,
       shiftReg       => (others => '0'),
       shiftCount     => (others => '0'),
+      asicRstL       => (others => '1'),
       clkCount       => (others => '0'),
       saciClkRising  => '0',
       saciClkFalling => '0',
@@ -124,7 +129,7 @@ begin
    -------------------------------------------------------------------------------------------------
    -- Main logic
    -------------------------------------------------------------------------------------------------
-   comb : process (addr, chip, cmd, op, r, req, saciRspSync, sysRst, wrData) is
+   comb : process (addr, asicRstL, chip, cmd, op, r, req, saciRspSync, sysRst, wrData) is
       variable v        : RegType;
       variable rspIndex : integer;
    begin
@@ -139,6 +144,7 @@ begin
       if (r.clkCount = SACI_CLK_HALF_PERIOD_C) then
          v.saciClk  := not r.saciClk;
          v.clkCount := (others => '0');
+         v.asicRstL := r.asicRstL(30 downto 0) & '1';
       end if;
 
       -- Create saciClk edge strobes
@@ -153,15 +159,20 @@ begin
          end if;
       end if;
 
+      -- Check for ASIC reset condition
+      if (asicRstL = '0') then
+         -- Reset the bus
+         v.asicRstL := (others => '0');
+      end if;
+
       case (r.state) is
          when IDLE_S =>
             v.fail       := '0';
             v.shiftReg   := (others => '0');
             v.shiftCount := (others => '0');
             v.saciSelL   := (others => '1');
-            -- Hold clock inactive while idle
-            -- Make this configurable?
-            if (not SACI_CLK_FREERUN_G) then
+            -- Hold clock inactive while idle else there is a ASIC reset
+            if (not SACI_CLK_FREERUN_G) and (r.asicRstL(31)='1') then
                v.saciClk  := '0';
                v.clkCount := (others => '0');
             end if;