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introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to pr…
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…epare for asic deployment
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@cbakalis-slac
cbakalis-slac committed Oct 1, 2024
1 parent de4825d commit 2bff33d
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Showing 16 changed files with 180 additions and 136 deletions.
19 changes: 10 additions & 9 deletions axi/axi-stream/rtl/AxiStreamDeMux.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@ use surf.AxiStreamPkg.all;
entity AxiStreamDeMux is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
NUM_MASTERS_G : integer range 1 to 256 := 12;
MODE_G : string := "INDEXED"; -- Or "ROUTED" Or "DYNAMIC"
Expand All @@ -36,10 +37,10 @@ entity AxiStreamDeMux is
port (
-- Clock and reset
axisClk : in sl;
axisRst : in sl;
axisRst : in sl := not RST_POLARITY_G;
-- Dynamic Route Table (only used when MODE_G = "DYNAMIC")
dynamicRouteMasks : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
-- Slave
sAxisMaster : in AxiStreamMasterType;
sAxisSlave : out AxiStreamSlaveType;
Expand Down Expand Up @@ -139,7 +140,7 @@ begin
sAxisSlave <= v.slave;

-- Reset
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -151,14 +152,14 @@ begin

end process comb;

GEN_VEC :
for i in (NUM_MASTERS_G-1) downto 0 generate
GEN_VEC : for i in (NUM_MASTERS_G-1) downto 0 generate

U_Pipeline : entity surf.AxiStreamPipeline
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
port map (
axisClk => axisClk,
axisRst => axisRst,
Expand All @@ -171,7 +172,7 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G and axisRst = '1') then
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axisClk) then
r <= rin after TPD_G;
Expand Down
14 changes: 8 additions & 6 deletions axi/axi-stream/rtl/AxiStreamMux.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ use surf.AxiStreamPkg.all;
entity AxiStreamMux is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
PIPE_STAGES_G : integer range 0 to 16 := 0;
NUM_SLAVES_G : integer range 1 to 256 := 4;
Expand Down Expand Up @@ -66,7 +67,7 @@ entity AxiStreamMux is
port (
-- Clock and reset
axisClk : in sl;
axisRst : in sl;
axisRst : in sl := not RST_POLARITY_G;
-- Slaves
disableSel : in slv(NUM_SLAVES_G-1 downto 0) := (others => '0');
rearbitrate : in sl := '0';
Expand Down Expand Up @@ -308,7 +309,7 @@ begin
sAxisSlaves <= v.slaves;

-- Reset
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -322,7 +323,7 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G) and (axisRst = '1') then
if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axisClk) then
r <= rin after TPD_G;
Expand All @@ -332,9 +333,10 @@ begin
-- Optional output pipeline registers to ease timing
AxiStreamPipeline_1 : entity surf.AxiStreamPipeline
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
port map (
axisClk => axisClk,
axisRst => axisRst,
Expand Down
7 changes: 4 additions & 3 deletions axi/axi-stream/rtl/AxiStreamPipeline.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,13 +23,14 @@ use surf.AxiStreamPkg.all;
entity AxiStreamPipeline is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
SIDE_BAND_WIDTH_G : positive := 1; -- General purpose sideband
PIPE_STAGES_G : natural := 0);
port (
-- Clock and Reset
axisClk : in sl;
axisRst : in sl;
axisRst : in sl := not RST_POLARITY_G;
-- Slave Port
sAxisMaster : in AxiStreamMasterType;
sSideBand : in slv(SIDE_BAND_WIDTH_G-1 downto 0) := (others => '0');
Expand Down Expand Up @@ -148,7 +149,7 @@ begin
mSideBand <= r.mSideBand(PIPE_STAGES_C);

-- Synchronous Reset
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -159,7 +160,7 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G and axisRst = '1') then
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axisClk) then
r <= rin after TPD_G;
Expand Down
7 changes: 4 additions & 3 deletions base/crc/rtl/Crc32.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,13 +34,14 @@ use surf.CrcPkg.all;
entity Crc32 is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
BYTE_WIDTH_G : positive := 4;
INPUT_REGISTER_G : boolean := true;
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF";
CRC_POLY_G : slv(31 downto 0) := x"04C11DB7");
port (
crcPwrOnRst : in sl := '0';
crcPwrOnRst : in sl := not RST_POLARITY_G;
crcOut : out slv(31 downto 0); -- CRC output
crcRem : out slv(31 downto 0); -- CRC interim remainder
crcClk : in sl; -- system clock
Expand Down Expand Up @@ -146,10 +147,10 @@ begin

seq : process (crcClk, crcPwrOnRst) is
begin
if (RST_ASYNC_G and crcPwrOnRst = '1') then
if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif (rising_edge(crcClk)) then
if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
else
r <= rin after TPD_G;
Expand Down
7 changes: 4 additions & 3 deletions base/crc/rtl/Crc32Parallel.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,12 +40,13 @@ use surf.CrcPkg.all;
entity Crc32Parallel is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
BYTE_WIDTH_G : positive := 4;
INPUT_REGISTER_G : boolean := true;
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF");
port (
crcPwrOnRst : in sl := '0';
crcPwrOnRst : in sl := not RST_POLARITY_G;
crcOut : out slv(31 downto 0); -- CRC output
crcRem : out slv(31 downto 0); -- CRC interim remainder
crcClk : in sl; -- system clock
Expand Down Expand Up @@ -188,10 +189,10 @@ begin

seq : process (crcClk, crcPwrOnRst) is
begin
if (RST_ASYNC_G and crcPwrOnRst = '1') then
if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif (rising_edge(crcClk)) then
if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
else
r <= rin after TPD_G;
Expand Down
2 changes: 1 addition & 1 deletion base/general/rtl/Gearbox.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ entity Gearbox is
port (
-- Clock and Reset
clk : in sl;
rst : in sl;
rst : in sl := not RST_POLARITY_G;
-- input side data and flow control
slaveData : in slv(SLAVE_WIDTH_G-1 downto 0);
slaveValid : in sl := '1';
Expand Down
7 changes: 4 additions & 3 deletions base/general/rtl/Scrambler.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all;
entity Scrambler is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
DIRECTION_G : string := "SCRAMBLER"; -- or DESCRAMBLER
DATA_WIDTH_G : integer := 64;
Expand All @@ -34,7 +35,7 @@ entity Scrambler is
TAPS_G : IntegerArray := (0 => 39, 1 => 58));
port (
clk : in sl;
rst : in sl;
rst : in sl := not RST_POLARITY_G;
inputValid : in sl := '1';
inputReady : out sl;
inputData : in slv(DATA_WIDTH_G-1 downto 0);
Expand Down Expand Up @@ -129,7 +130,7 @@ begin
inputReady <= v.inputReady;

-- Reset
if (RST_ASYNC_G = false and rst = '1') then
if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -150,7 +151,7 @@ begin

seq : process (clk, rst) is
begin
if (RST_ASYNC_G and rst = '1') then
if (RST_ASYNC_G and rst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(clk) then
r <= rin after TPD_G;
Expand Down
40 changes: 21 additions & 19 deletions base/sync/rtl/SynchronizerFifo.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,18 +22,19 @@ use surf.StdRtlPkg.all;

entity SynchronizerFifo is
generic (
TPD_G : time := 1 ns;
RST_ASYNC_G : boolean := false;
COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration
MEMORY_TYPE_G : string := "distributed";
SYNC_STAGES_G : integer range 3 to (2**24) := 3;
PIPE_STAGES_G : natural range 0 to 16 := 0;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
ADDR_WIDTH_G : integer range 2 to 48 := 4;
INIT_G : slv := "0");
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration
MEMORY_TYPE_G : string := "distributed";
SYNC_STAGES_G : integer range 3 to (2**24) := 3;
PIPE_STAGES_G : natural range 0 to 16 := 0;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
ADDR_WIDTH_G : integer range 2 to 48 := 4;
INIT_G : slv := "0");
port (
-- Asynchronous Reset
rst : in sl := '0';
rst : in sl := not RST_POLARITY_G;
-- Write Ports (wr_clk domain)
wr_clk : in sl;
wr_en : in sl := '1';
Expand All @@ -58,15 +59,16 @@ begin

FifoAsync_1 : entity surf.FifoAsync
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
FWFT_EN_G => true,
SYNC_STAGES_G => SYNC_STAGES_G,
PIPE_STAGES_G => PIPE_STAGES_G,
DATA_WIDTH_G => DATA_WIDTH_G,
ADDR_WIDTH_G => ADDR_WIDTH_G,
INIT_G => INIT_C)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
FWFT_EN_G => true,
SYNC_STAGES_G => SYNC_STAGES_G,
PIPE_STAGES_G => PIPE_STAGES_G,
DATA_WIDTH_G => DATA_WIDTH_G,
ADDR_WIDTH_G => ADDR_WIDTH_G,
INIT_G => INIT_C)
port map (
rst => rst,
wr_clk => wr_clk,
Expand Down
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