more code clean up

slaclab · Jun 13, 2023 · 484b2b7 · 484b2b7
1 parent d4ae1f1
commit 484b2b7
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Showing 2 changed files with 5 additions and 6 deletions.
diff --git a/protocols/pgp/shared/PgpXvcWrapper.vhd b/protocols/pgp/shared/PgpXvcWrapper.vhd
@@ -46,9 +46,9 @@ end PgpXvcWrapper;
 
 architecture rtl of PgpXvcWrapper is
 
-   signal ibXvcMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+   signal ibXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C);
    signal ibXvcSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
-   signal obXvcMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+   signal obXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C);
    signal obXvcSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
 
 begin

diff --git a/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd b/protocols/xvc-udp/rtl/DmaXvcWrapper.vhd
@@ -39,14 +39,14 @@ entity DmaXvcWrapper is
       -- Clock and Reset (xvcClk domain)
       xvcClk       : in  sl;
       xvcRst       : in  sl;
-      -- Clock and Reset (pgpClk domain)
+      -- Clock and Reset (axisClk domain)
       axisClk      : in  sl;
       axisRst      : in  sl;
-      -- OB FIFO
+      -- OB FIFO (axisClk domain)
       obFifoMaster : in  AxiStreamMasterType;
       obFifoSlave  : out AxiStreamSlaveType;
       obFifoCtrl   : out AxiStreamCtrlType;
-      -- IB FIFO
+      -- IB FIFO (axisClk domain)
       ibFifoSlave  : in  AxiStreamSlaveType;
       ibFifoMaster : out AxiStreamMasterType);
 end DmaXvcWrapper;
@@ -133,5 +133,4 @@ begin
          mAxisMaster => ibFifoMaster,
          mAxisSlave  => ibFifoSlave);
 
-
 end rtl;