Allow some DDC registers to be set via yaml

slaclab · Jun 15, 2023 · 5c4a176 · 5c4a176
1 parent 7480bf9
commit 5c4a176
Show file tree

Hide file tree

Showing 2 changed files with 17 additions and 7 deletions.
diff --git a/python/surf/devices/ti/_Adc32Rf45.py b/python/surf/devices/ti/_Adc32Rf45.py
@@ -17,7 +17,7 @@
 import rogue
 
 class Adc32Rf45(pr.Device):
-    def __init__( self, verify=True, DDC0_NC01_MSB=0x4e, **kwargs):
+    def __init__( self, verify=True, **kwargs):
 
         self._useVars = rogue.Version.greaterThanEqual('5.4.0')
 
@@ -1067,12 +1067,14 @@ def JESD_DDC_config():
                 channel.DECIM_FACTOR.set(0x0,write=True)
                 channel.DUAL_BAND_EN.set(0x0,write=True)
                 channel.REAL_OUT_EN.set(0x0,write=True)
-                channel.DDC0_NCO1_LSB.set(0x00,write=True)
-                channel.DDC0_NCO1_MSB.set(DDC0_NC01_MSB, write=True)
-                channel.DDC0_NCO2_LSB.set(0x00,write=True)
-                channel.DDC0_NCO2_MSB.set(0x00,write=True)
-                channel.DDC0_NCO3_LSB.set(0x00,write=True)
-                channel.DDC0_NCO3_MSB.set(0x00,write=True)
+                # Write the value that has been loaded via yaml,
+                # or write the default value defined in _AdcRf45Channel.py
+                channel.DDC0_NCO1_LSB.write()
+                channel.DDC0_NCO1_MSB.write()
+                channel.DDC0_NCO2_LSB.write()
+                channel.DDC0_NCO2_MSB.write()
+                channel.DDC0_NCO3_LSB.write()
+                channel.DDC0_NCO3_MSB.write()
                 channel.NCO_SEL_PIN.set(0x00,write=True)
                 channel.NCO_SEL.set(0x00,write=True)
                 channel.LMFC_RESET_MODE.set(0x00,write=True)

diff --git a/python/surf/devices/ti/_Adc32Rf45Channel.py b/python/surf/devices/ti/_Adc32Rf45Channel.py
@@ -585,6 +585,7 @@ def __init__( self, verify=True, **kwargs):
             bitOffset    =  0,
             base         = pr.UInt,
             mode         = "RW",
+            value        = 0x00,
             verify       = verify,
             overlapEn    = True,
         ))
@@ -598,6 +599,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 04e, # 748.8 Mhz
             overlapEn    = True,
         ))
 
@@ -610,6 +612,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 0x00,
             overlapEn    = True,
         ))
 
@@ -622,6 +625,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 0x00,
             overlapEn    = True,
         ))
 
@@ -634,6 +638,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 0x00,
             overlapEn    = True,
         ))
 
@@ -646,6 +651,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 0x00,
             overlapEn    = True,
         ))
 
@@ -658,6 +664,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 0x00,
             overlapEn    = True,
         ))
 
@@ -670,6 +677,7 @@ def __init__( self, verify=True, **kwargs):
             base         = pr.UInt,
             mode         = "RW",
             verify       = verify,
+            value        = 0x00,
             overlapEn    = True,
         ))