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Merge pull request #1145 from slaclab/pre-release
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Release Candidate v2.47.2
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@ruck314
ruck314 committed Apr 17, 2024
2 parents ffd8b71 + 04b9f63 commit 6995288
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Showing 15 changed files with 295 additions and 151 deletions.
5 changes: 5 additions & 0 deletions axi/axi-stream/rtl/AxiStreamFifoV2.vhd
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Expand Up @@ -313,7 +313,12 @@ begin
-- Start output when a block or end of frame is available
elsif fifoValidLast = '1' or (VALID_THOLD_G /= 0 and fifoRdCount >= VALID_THOLD_G) then
fifoInFrame <= '1' after TPD_G;

-- Prevent the FIFO from locking up when frame deeper than what the U_Fifo can hold
elsif (fifoAFull = '1') then
fifoInFrame <= '1' after TPD_G;
end if;

end if;
end process;

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19 changes: 10 additions & 9 deletions devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd
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Expand Up @@ -24,14 +24,14 @@ use surf.I2cPkg.all;

entity Sc18Is602Core is
generic (
TPD_G : time := 1 ns;
I2C_BASE_ADDR_G : slv(2 downto 0) := "000"; -- A[2:0] pin config
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
SDO_MUX_SEL_MAP_G : Slv2Array(3 downto 0) := (0 => "00", 1 => "01", 2 => "10", 3 => "11");
ADDRESS_SIZE_G : IntegerArray(3 downto 0) := (others => 7); -- SPI Address bits per channel
DATA_SIZE_G : IntegerArray(3 downto 0) := (others => 16); -- SPI Data bits per channel
AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
TPD_G : time := 1 ns;
I2C_BASE_ADDR_G : slv(2 downto 0) := "000"; -- A[2:0] pin config
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
SDO_MUX_SEL_MAP_G : Slv2Array(3 downto 0) := (0 => "00", 1 => "01", 2 => "10", 3 => "11");
ADDRESS_SIZE_G : IntegerArray(3 downto 0) := (others => 7); -- SPI Address bits per channel
DATA_SIZE_G : IntegerArray(3 downto 0) := (others => 16); -- SPI Data bits per channel
AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
port (
-- I2C Ports
i2ci : in i2c_in_type;
Expand Down Expand Up @@ -90,7 +90,8 @@ architecture rtl of Sc18Is602Core is
regReq => '0',
busReq => '0',
endianness => '1', -- Big endian
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type StateType is (
IDLE_S,
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11 changes: 6 additions & 5 deletions devices/Silabs/si5394/rtl/Si5394I2cCore.vhd
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Expand Up @@ -25,8 +25,8 @@ use surf.I2cPkg.all;
entity Si5394I2cCore is
generic (
TPD_G : time := 1 ns;
MEMORY_INIT_FILE_G : string := "none"; -- Used to initialization boot ROM
I2C_BASE_ADDR_G : slv(1 downto 0) := "00"; -- A[1:0] pin config
MEMORY_INIT_FILE_G : string := "none"; -- Used to initialization boot ROM
I2C_BASE_ADDR_G : slv(1 downto 0) := "00"; -- A[1:0] pin config
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
AXIL_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
Expand Down Expand Up @@ -84,7 +84,8 @@ architecture rtl of Si5394I2cCore is
regReq => '0',
busReq => '0',
endianness => '0',
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type StateType is (
POR_WAIT_S,
Expand Down Expand Up @@ -422,8 +423,8 @@ begin
generic map(
TPD_G => TPD_G,
DURATION_G => getTimeRatio(100.0E-9, (1.0/AXIL_CLK_FREQ_G)), -- min 100 ns pulse
IN_POLARITY_G => '1', -- active HIGH input
OUT_POLARITY_G => '0') -- active LOW output
IN_POLARITY_G => '1', -- active HIGH input
OUT_POLARITY_G => '0') -- active LOW output
port map (
clk => axilClk,
arst => axilRst,
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18 changes: 14 additions & 4 deletions ethernet/UdpEngine/rtl/UdpEngineWrapper.vhd
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Expand Up @@ -51,6 +51,8 @@ entity UdpEngineWrapper is
-- Local Configurations
localMac : in slv(47 downto 0); -- big-Endian configuration
localIp : in slv(31 downto 0); -- big-Endian configuration
softMac : out slv(47 downto 0); -- big-Endian configuration
softIp : out slv(31 downto 0); -- big-Endian configuration
-- Remote Configurations
clientRemotePort : in Slv16Array(CLIENT_SIZE_G-1 downto 0) := (others => x"0000");
clientRemoteIp : in Slv32Array(CLIENT_SIZE_G-1 downto 0) := (others => x"00000000");
Expand Down Expand Up @@ -82,6 +84,8 @@ end UdpEngineWrapper;
architecture rtl of UdpEngineWrapper is

type RegType is record
softMac : slv(47 downto 0);
softIp : slv(31 downto 0);
broadcastIp : slv(31 downto 0);
igmpIp : Slv32Array(IGMP_GRP_SIZE-1 downto 0);
clientRemotePort : Slv16Array(CLIENT_SIZE_G-1 downto 0);
Expand All @@ -91,6 +95,8 @@ architecture rtl of UdpEngineWrapper is
end record;

constant REG_INIT_C : RegType := (
softMac => (others => '0'),
softIp => (others => '0'),
broadcastIp => (others => '0'),
igmpIp => IGMP_INIT_G,
clientRemotePort => (others => (others => '0')),
Expand Down Expand Up @@ -240,13 +246,21 @@ begin
for i in IGMP_GRP_SIZE-1 downto 0 loop
axiSlaveRegister(regCon, toSlv((4*i)+4048, 12), 0, v.igmpIp(i)); -- big-Endian configuration
end loop;
axiSlaveRegister (regCon, x"FE4", 0, v.softIp);
axiSlaveRegister (regCon, x"FE8", 0, v.softMac);
axiSlaveRegister (regCon, x"FF0", 0, v.broadcastIp);
axiSlaveRegisterR(regCon, x"FF4", 0, dhcpIp);
axiSlaveRegisterR(regCon, x"FF8", 0, localMac);

-- Closeout the transaction
axiSlaveDefault(regCon, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C);

-- Outputs
axilWriteSlave <= r.axilWriteSlave;
axilReadSlave <= r.axilReadSlave;
softIp <= r.softIp;
softMac <= r.softMac;

-- Synchronous Reset
if (rst = '1') then
v := REG_INIT_C;
Expand All @@ -261,10 +275,6 @@ begin
-- Register the variable for next clock cycle
rin <= v;

-- Outputs
axilWriteSlave <= r.axilWriteSlave;
axilReadSlave <= r.axilReadSlave;

end process comb;

seq : process (clk) is
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71 changes: 48 additions & 23 deletions protocols/batcher/rtl/AxiStreamBatcherAxil.vhd
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Expand Up @@ -13,49 +13,50 @@
-- copied, modified, propagated, or distributed except according to the terms
-- contained in the LICENSE.txt file.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


library surf;
use surf.StdRtlPkg.all;
use surf.AxiStreamPkg.all;
use surf.AxiLitePkg.all;

entity AxiStreamBatcherAxil is

generic (
TPD_G : time := 1 ns;
COMMON_CLOCK_G : boolean := false;
MAX_NUMBER_SUB_FRAMES_G : positive := 32;
SUPER_FRAME_BYTE_THRESHOLD_G : natural := 8192;
MAX_CLK_GAP_G : natural := 256;
TPD_G : time := 1 ns;
COMMON_CLOCK_G : boolean := false;
MAX_NUMBER_SUB_FRAMES_G : positive := 32;
SUPER_FRAME_BYTE_THRESHOLD_G : natural := 8192;
MAX_CLK_GAP_G : natural := 256;
AXIS_CONFIG_G : AxiStreamConfigType;
INPUT_PIPE_STAGES_G : natural := 0;
OUTPUT_PIPE_STAGES_G : natural := 1);

INPUT_PIPE_STAGES_G : natural := 0;
OUTPUT_PIPE_STAGES_G : natural := 1);
port (
-- AXIS Interfaces (axisClk domain)
axisClk : in sl;
axisRst : in sl;
idle : out sl;
sAxisMaster : in AxiStreamMasterType;
sAxisSlave : out AxiStreamSlaveType;
mAxisMaster : out AxiStreamMasterType;
mAxisSlave : in AxiStreamSlaveType;
-- AXI-Lite Interface (axilClk domain)
axilClk : in sl;
axilRst : in sl;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType);

end entity AxiStreamBatcherAxil;

architecture rtl of AxiStreamBatcherAxil is

type RegType is record
softRst : sl;
blowoff : sl;
superFrameByteThreshold : slv(31 downto 0);
maxSubFrames : slv(15 downto 0);
maxClkGap : slv(31 downto 0);
Expand All @@ -64,6 +65,8 @@ architecture rtl of AxiStreamBatcherAxil is
end record RegType;

constant REG_INIT_C : RegType := (
softRst => '0',
blowoff => '0',
superFrameByteThreshold => toSlv(SUPER_FRAME_BYTE_THRESHOLD_G, 32),
maxSubFrames => toSlv(MAX_NUMBER_SUB_FRAMES_G, 16),
maxClkGap => toSlv(MAX_CLK_GAP_G, 32),
Expand All @@ -78,9 +81,15 @@ architecture rtl of AxiStreamBatcherAxil is
signal syncAxilWriteMaster : AxiLiteWriteMasterType;
signal syncAxilWriteSlave : AxiLiteWriteSlaveType;

signal axisReset : sl;
signal batcherIdle : sl;
signal sAxisSlaveTmp : AxiStreamSlaveType;

begin

U_AxiStreamBatcher_1 : entity surf.AxiStreamBatcher
idle <= batcherIdle;

U_AxiStreamBatcher : entity surf.AxiStreamBatcher
generic map (
TPD_G => TPD_G,
MAX_NUMBER_SUB_FRAMES_G => MAX_NUMBER_SUB_FRAMES_G,
Expand All @@ -91,17 +100,17 @@ begin
OUTPUT_PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G)
port map (
axisClk => axisClk, -- [in]
axisRst => axisRst, -- [in]
axisRst => axisReset, -- [in]
superFrameByteThreshold => r.superFrameByteThreshold, -- [in]
maxSubFrames => r.maxSubFrames, -- [in]
maxClkGap => r.maxClkGap, -- [in]
idle => idle, -- [out]
idle => batcherIdle, -- [out]
sAxisMaster => sAxisMaster, -- [in]
sAxisSlave => sAxisSlave, -- [out]
sAxisSlave => sAxisSlaveTmp, -- [out]
mAxisMaster => mAxisMaster, -- [out]
mAxisSlave => mAxisSlave); -- [in]

U_AxiLiteAsync_1 : entity surf.AxiLiteAsync
U_AxiLiteAsync : entity surf.AxiLiteAsync
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => COMMON_CLOCK_G)
Expand All @@ -119,26 +128,43 @@ begin
mAxiWriteMaster => syncAxilWriteMaster, -- [out]
mAxiWriteSlave => r.axilWriteSlave); -- [in]

comb : process (axisRst, r, syncAxilReadMaster, syncAxilWriteMaster) is
comb : process (axisRst, batcherIdle, r, sAxisSlaveTmp, syncAxilReadMaster,
syncAxilWriteMaster) is
variable v : RegType;
variable axilEp : AxiLiteEndpointType;
begin
-- Latch the current value
v := r;

-- Reset strobes
v.softRst := '0';

-- Determine the transaction type
axiSlaveWaitTxn(axilEp, syncAxilWriteMaster, syncAxilReadMaster, v.axilWriteSlave, v.axilReadSlave);

axiSlaveRegister(axilEp, X"00", 0, v.superFrameByteThreshold);
axiSlaveRegister(axilEp, X"04", 0, v.maxSubFrames);
axiSlaveRegister(axilEp, X"08", 0, v.maxClkGap);
-- Map the registers
axiSlaveRegister (axilEp, X"00", 0, v.superFrameByteThreshold);
axiSlaveRegister (axilEp, X"04", 0, v.maxSubFrames);
axiSlaveRegister (axilEp, X"08", 0, v.maxClkGap);
axiSlaveRegisterR(axilEp, X"0C", 0, batcherIdle);
axiSlaveRegister (axilEp, x"F8", 0, v.blowOff);
axiSlaveRegister (axilEp, x"FC", 0, v.softRst);

-- Closeout the transaction
axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C);

rin <= v;
-- Outputs
axisReset <= axisRst or r.softRst or r.blowOff;
sAxisSlave.tReady <= sAxisSlaveTmp.tReady or r.blowOff;

-- Reset
if (axisRst = '1') then
v := REG_INIT_C;
end if;

-- Register the variable for next clock cycle
rin <= v;

end process comb;

seq : process (axisClk) is
Expand All @@ -148,5 +174,4 @@ begin
end if;
end process seq;

end architecture rtl;

end rtl;
17 changes: 9 additions & 8 deletions protocols/i2c/axi/AxiI2cEepromCore.vhd
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Expand Up @@ -36,13 +36,13 @@ use surf.I2cPkg.all;

entity AxiI2cEepromCore is
generic (
TPD_G : time := 1 ns;
ADDR_WIDTH_G : positive := 16;
POLL_TIMEOUT_G : positive := 16;
I2C_ADDR_G : slv(6 downto 0) := "1010000";
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
TPD_G : time := 1 ns;
ADDR_WIDTH_G : positive := 16;
POLL_TIMEOUT_G : positive := 16;
I2C_ADDR_G : slv(6 downto 0) := "1010000";
I2C_SCL_FREQ_G : real := 100.0E+3; -- units of Hz
I2C_MIN_PULSE_G : real := 100.0E-9; -- units of seconds
AXI_CLK_FREQ_G : real := 156.25E+6); -- units of Hz
port (
-- I2C Ports
i2ci : in i2c_in_type;
Expand Down Expand Up @@ -82,7 +82,8 @@ architecture rtl of AxiI2cEepromCore is
regReq => '0',
busReq => '0',
endianness => '1', -- Big endian
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type StateType is (
IDLE_S,
Expand Down
3 changes: 2 additions & 1 deletion protocols/i2c/axi/AxiLiteCrossbarI2cMux.vhd
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Expand Up @@ -85,7 +85,8 @@ architecture mapping of AxiLiteCrossbarI2cMux is
regReq => '0',
busReq => '0',
endianness => DEVICE_MAP_C.endianness,
repeatStart => DEVICE_MAP_C.repeatStart);
repeatStart => DEVICE_MAP_C.repeatStart,
wrDataOnRd => '0');

type StateType is (
IDLE_S,
Expand Down
4 changes: 3 additions & 1 deletion protocols/i2c/rtl/I2cPkg.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ package I2cPkg is
busReq : sl;
endianness : sl;
repeatStart : sl;
wrDataOnRd : sl;
end record;

constant I2C_REG_MASTER_IN_INIT_C : I2cRegMasterInType := (
Expand All @@ -104,7 +105,8 @@ package I2cPkg is
regReq => '0',
busReq => '0',
endianness => '0',
repeatStart => '0');
repeatStart => '0',
wrDataOnRd => '0');

type I2cRegMasterInArray is array (natural range <>) of I2cRegMasterInType;

Expand Down
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