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minor fixes to test_AxiVersionIpIntegrator.py
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@ruck314
ruck314 committed Jul 3, 2023
1 parent 96b2c83 commit 7639ef3
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Showing 3 changed files with 85 additions and 35 deletions.
12 changes: 6 additions & 6 deletions axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -96,13 +96,13 @@ entity AxiStreamFifoV2IpIntegrator is
M_AXIS_ACLK : in std_logic := '0';
M_AXIS_ARESETN : in std_logic := '0';
M_AXIS_TVALID : out std_logic;
M_AXIS_TDATA : out std_logic_vector((8*S_TDATA_NUM_BYTES)-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(S_TDATA_NUM_BYTES-1 downto 0);
M_AXIS_TDATA : out std_logic_vector((8*M_TDATA_NUM_BYTES)-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(M_TDATA_NUM_BYTES-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(M_TDATA_NUM_BYTES-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TDEST : out std_logic_vector(S_TDEST_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(S_TID_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(S_TUSER_WIDTH-1 downto 0);
M_AXIS_TDEST : out std_logic_vector(M_TDEST_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(M_TID_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(M_TUSER_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic := '1';
-- Misc. Interfaces
fifoPauseThresh : in std_logic_vector(FIFO_ADDR_WIDTH-1 downto 0) := (others => '1');
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102 changes: 76 additions & 26 deletions tests/test_AxiStreamFifoV2IpIntegrator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -9,14 +9,14 @@
##############################################################################

# dut_tb
import itertools
import logging
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory

from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor
from cocotbext.axi import AxiStreamFrame, AxiStreamBus, AxiStreamSource, AxiStreamSink

# test_AxiStreamFifoV2IpIntegrator
from cocotb_test.simulator import run
Expand All @@ -35,25 +35,25 @@ def __init__(self, dut):

# Start S_AXIS_ACLK clock (200 MHz) in a separate thread
cocotb.start_soon(Clock(dut.S_AXIS_ACLK, 5.0, units='ns').start())

# Start M_AXIS_ACLK clock (200 MHz) in a separate thread
cocotb.start_soon(Clock(dut.M_AXIS_ACLK, 5.0, units='ns').start())
cocotb.start_soon(Clock(dut.M_AXIS_ACLK, 5.0, units='ns').start())

# Setup the AXI stream source
self.source = AxiStreamSource(
bus = AxiStreamBus.from_prefix(dut, "S_AXIS"),
clock = dut.S_AXIS_ACLK,
bus = AxiStreamBus.from_prefix(dut, "S_AXIS"),
clock = dut.S_AXIS_ACLK,
reset = dut.S_AXIS_ARESETN,
reset_active_level = False,
)

# Setup the AXI stream sink
self.sink = AxiStreamSink(
bus = AxiStreamBus.from_prefix(dut, "M_AXIS"),
clock = dut.M_AXIS_ACLK,
bus = AxiStreamBus.from_prefix(dut, "M_AXIS"),
clock = dut.M_AXIS_ACLK,
reset = dut.M_AXIS_ARESETN,
reset_active_level = False,
)
)

def set_idle_generator(self, generator=None):
if generator:
Expand All @@ -73,7 +73,7 @@ async def s_cycle_reset(self):
self.dut.S_AXIS_ARESETN.value = 1
await RisingEdge(self.dut.S_AXIS_ACLK)
await RisingEdge(self.dut.S_AXIS_ACLK)

async def m_cycle_reset(self):
self.dut.M_AXIS_ARESETN.setimmediatevalue(0)
await RisingEdge(self.dut.M_AXIS_ACLK)
Expand All @@ -83,28 +83,78 @@ async def m_cycle_reset(self):
await RisingEdge(self.dut.M_AXIS_ACLK)
self.dut.M_AXIS_ARESETN.value = 1
await RisingEdge(self.dut.M_AXIS_ACLK)
await RisingEdge(self.dut.M_AXIS_ACLK)
await RisingEdge(self.dut.M_AXIS_ACLK)

async def dut_tb(dut):
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):

# Initialize the DUT
tb = TB(dut)

# Reset DUT
id_count = 2**len(tb.source.bus.tid)

cur_id = 1

await tb.s_cycle_reset()
await tb.m_cycle_reset()

tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)

test_frames = []

for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
await tb.source.send(test_frame)

test_frames.append(test_frame)

cur_id = (cur_id + 1) % id_count

for test_frame in test_frames:
rx_frame = await tb.sink.recv()

assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser

assert tb.sink.empty()

def cycle_pause():
return itertools.cycle([1, 1, 1, 0])

def size_list():
return list(range(1, 32+1))

def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))

if cocotb.SIM_NAME:
factory = TestFactory(dut_tb)
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()

tests_dir = os.path.dirname(__file__)
tests_module = 'AxiStreamFifoV2IpIntegrator'

@pytest.mark.parametrize(
"parameters", [
{'S_TDATA_NUM_BYTES': '1', },
])
##############################################################################

paramSweep = []
for sTdataByte in ['2','6']:
for mTdataByte in ['2','6']:
tmpDict = {
"M_TDATA_NUM_BYTES": mTdataByte,
"S_TDATA_NUM_BYTES": sTdataByte,
}
paramSweep.append(tmpDict)

##############################################################################

@pytest.mark.parametrize("parameters", paramSweep)
def test_AxiStreamFifoV2IpIntegrator(parameters):

# https://github.com/themperek/cocotb-test#arguments-for-simulatorrun
Expand Down Expand Up @@ -132,19 +182,19 @@ def test_AxiStreamFifoV2IpIntegrator(parameters):
parameters = parameters,

# The directory used to compile the tests. (default: sim_build)
sim_build = f'{tests_dir}/sim_build/{tests_module}',
sim_build = f'{tests_dir}/sim_build/{tests_module}.' + ",".join((f"{key}={value}" for key, value in parameters.items())),

# A dictionary of extra environment variables set in simulator process.
extra_env=parameters,

# Select a simulator
simulator="ghdl",

# use of synopsys package "std_logic_arith" needs the -fsynopsys option
# -frelaxed-rules option to allow IP integrator attributes
# When two operators are overloaded, give preference to the explicit declaration (-fexplicit)
vhdl_compile_args = ['-fsynopsys','-frelaxed-rules', '-fexplicit'],

# Select a simulator
simulator="ghdl",

# # Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd)
# sim_args =[f'--vcd={tests_module}.vcd'],
# Dump waveform to file ($ gtkwave sim_build/AxiStreamFifoV2IpIntegrator/AxiStreamFifoV2IpIntegrator.vcd)
sim_args =[f'--vcd={tests_module}.vcd'],
)
6 changes: 3 additions & 3 deletions tests/test_AxiVersionIpIntegrator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -123,13 +123,13 @@ def test_AxiVersionIpIntegrator(parameters):
# A dictionary of extra environment variables set in simulator process.
extra_env=parameters,

# Select a simulator
simulator="ghdl",

# use of synopsys package "std_logic_arith" needs the -fsynopsys option
# -frelaxed-rules option to allow IP integrator attributes
vhdl_compile_args = ['-fsynopsys','-frelaxed-rules'],

# Select a simulator
simulator="ghdl",

# Dump waveform to file ($ gtkwave sim_build/AxiVersionIpIntegrator/AxiVersionIpIntegrator.vcd)
sim_args =[f'--vcd={tests_module}.vcd'],
)

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