first commit of rst_polarity switch to boolean; only touch the files …

…used by the asic synthesis tool for now

base/fifo/rtl/FifoOutputPipeline.vhd

@@ -22,7 +22,7 @@ use surf.StdRtlPkg.all;
 entity FifoOutputPipeline is
    generic (
       TPD_G          : time                       := 1 ns;
-      RST_POLARITY_G : sl                         := '1';  -- '1' for active high rst, '0' for active low
+      RST_POLARITY_G : boolean                    := true;  -- true for active high rst, false for active low
       RST_ASYNC_G    : boolean                    := false;
       DATA_WIDTH_G   : integer range 1 to (2**24) := 16;
       PIPE_STAGES_G  : natural range 0 to 16      := 1);
@@ -37,7 +37,7 @@ entity FifoOutputPipeline is
       mRdEn  : in  sl;
       -- Clock and Reset
       clk    : in  sl;
-      rst    : in  sl := not RST_POLARITY_G);              -- Optional reset
+      rst    : in  sl := not toSl(RST_POLARITY_G));              -- Optional reset
 end FifoOutputPipeline;
 
 architecture rtl of FifoOutputPipeline is
@@ -143,7 +143,7 @@ begin
          end if;
 
          -- Synchronous Reset
-         if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
+         if (RST_ASYNC_G = false and rst = toSl(RST_POLARITY_G)) then
             v := REG_INIT_C;
          end if;
 
@@ -159,7 +159,7 @@ begin
 
       seq : process (clk, rst) is
       begin
-         if (RST_ASYNC_G and rst = RST_POLARITY_G) then
+         if (RST_ASYNC_G and rst = toSl(RST_POLARITY_G)) then
             r <= REG_INIT_C after TPD_G;
          elsif rising_edge(clk) then
             r <= rin after TPD_G;

base/fifo/rtl/inferred/FifoAsync.vhd

@@ -23,7 +23,7 @@ use surf.StdRtlPkg.all;
 entity FifoAsync is
    generic (
       TPD_G          : time     := 1 ns;
-      RST_POLARITY_G : sl       := '1';  -- '1' for active high rst, '0' for active low
+      RST_POLARITY_G : boolean  := true;  -- true for active high rst, false for active low
       RST_ASYNC_G    : boolean  := false;
       MEMORY_TYPE_G  : string   := "block";
       BYP_RAM_G      : boolean  := false;

base/fifo/rtl/inferred/FifoRdFsm.vhd

@@ -23,7 +23,7 @@ use surf.StdRtlPkg.all;
 entity FifoRdFsm is
    generic (
       TPD_G          : time     := 1 ns;
-      RST_POLARITY_G : sl       := '1';  -- '1' for active high rst, '0' for active low
+      RST_POLARITY_G : boolean  := true;  -- true for active high rst, false for active low
       RST_ASYNC_G    : boolean  := false;
       FIFO_ASYNC_G   : boolean  := false;
       MEMORY_TYPE_G  : string   := "block";
@@ -298,7 +298,7 @@ begin
    ASYNC_RST : if (RST_ASYNC_G) generate
       seq : process (rd_clk, rst) is
       begin
-         if (rst = RST_POLARITY_G) then
+         if (rst = toSl(RST_POLARITY_G)) then
             r <= REG_INIT_C after TPD_G;
          elsif (rising_edge(rd_clk)) then
             r <= rin after TPD_G;
@@ -310,7 +310,7 @@ begin
       seq : process (rd_clk) is
       begin
          if (rising_edge(rd_clk)) then
-            if (rst = RST_POLARITY_G) then
+            if (rst = toSl(RST_POLARITY_G)) then
                r <= REG_INIT_C after TPD_G;
             else
                r <= rin after TPD_G;

base/fifo/rtl/inferred/FifoSync.vhd

@@ -23,7 +23,7 @@ use surf.StdRtlPkg.all;
 entity FifoSync is
    generic (
       TPD_G          : time     := 1 ns;
-      RST_POLARITY_G : sl       := '1';  -- '1' for active high rst, '0' for active low
+      RST_POLARITY_G : boolean  := true;  -- true for active high rst, false for active low
       RST_ASYNC_G    : boolean  := false;
       MEMORY_TYPE_G  : string   := "block";
       BYP_RAM_G      : boolean  := false;
@@ -35,7 +35,7 @@ entity FifoSync is
       FULL_THRES_G   : positive := 1;
       EMPTY_THRES_G  : positive := 1);
    port (
-      rst          : in  sl := not RST_POLARITY_G;
+      rst          : in  sl := not toSl(RST_POLARITY_G);
       clk          : in  sl;
       wr_en        : in  sl;
       rd_en        : in  sl;

base/fifo/rtl/inferred/FifoWrFsm.vhd

@@ -23,7 +23,7 @@ use surf.StdRtlPkg.all;
 entity FifoWrFsm is
    generic (
       TPD_G          : time     := 1 ns;
-      RST_POLARITY_G : sl       := '1';  -- '1' for active high rst, '0' for active low
+      RST_POLARITY_G : boolean  := true;  -- true for active high rst, false for active low
       RST_ASYNC_G    : boolean  := false;
       FIFO_ASYNC_G   : boolean  := false;
       DATA_WIDTH_G   : positive := 16;
@@ -214,7 +214,7 @@ begin
    ASYNC_RST : if (RST_ASYNC_G) generate
       seq : process (rst, wr_clk) is
       begin
-         if (rst = RST_POLARITY_G) then
+         if (rst = toSl(RST_POLARITY_G)) then
             r <= REG_INIT_C after TPD_G;
          elsif (rising_edge(wr_clk)) then
             r <= rin after TPD_G;
@@ -226,7 +226,7 @@ begin
       seq : process (wr_clk) is
       begin
          if (rising_edge(wr_clk)) then
-            if (rst = RST_POLARITY_G) then
+            if (rst = toSl(RST_POLARITY_G)) then
                r <= REG_INIT_C after TPD_G;
             else
                r <= rin after TPD_G;

base/ram/inferred/SimpleDualPortRam.vhd

@@ -23,7 +23,7 @@ use surf.StdRtlPkg.all;
 entity SimpleDualPortRam is
    generic (
       TPD_G          : time                       := 1 ns;
-      RST_POLARITY_G : sl                         := '1';  -- '1' for active high rst, '0' for active low
+      RST_POLARITY_G : boolean                    := true;  -- true for active high rst, false for active low
       RST_ASYNC_G    : boolean                    := false;
       MEMORY_TYPE_G  : string                     := "block";
       DOB_REG_G      : boolean                    := false;  -- Extra reg on doutb (folded into BRAM)
@@ -44,7 +44,7 @@ entity SimpleDualPortRam is
       clkb    : in  sl                                                    := '0';
       enb     : in  sl                                                    := '1';
       regceb  : in  sl                                                    := '1';
-      rstb    : in  sl                                                    := not(RST_POLARITY_G);
+      rstb    : in  sl                                                    := not(toSl(RST_POLARITY_G));
       addrb   : in  slv(ADDR_WIDTH_G-1 downto 0)                          := (others => '0');
       doutb   : out slv(DATA_WIDTH_G-1 downto 0));
 end SimpleDualPortRam;
@@ -105,10 +105,10 @@ begin
    -- Port B
    process(clkb, rstb)
    begin
-      if (RST_ASYNC_G and rstb = RST_POLARITY_G) then
+      if (RST_ASYNC_G and rstb = toSl(RST_POLARITY_G)) then
          doutbInt <= INIT_C after TPD_G;
       elsif rising_edge(clkb) then
-         if (RST_ASYNC_G = false and rstb = RST_POLARITY_G) then
+         if (RST_ASYNC_G = false and rstb = toSl(RST_POLARITY_G)) then
             doutbInt <= INIT_C after TPD_G;
          elsif enb = '1' then
             doutBInt <= mem(conv_integer(addrb)) after TPD_G;

base/sync/rtl/RstSync.vhd

@@ -22,8 +22,8 @@ use surf.StdRtlPkg.all;
 entity RstSync is
    generic (
       TPD_G           : time                             := 1 ns;   -- Simulation FF output delay
-      IN_POLARITY_G   : sl                               := '1';  -- 0 for active low rst, 1 for high
-      OUT_POLARITY_G  : sl                               := '1';
+      IN_POLARITY_G   : boolean                          := true;  -- false for active low rst, true for high
+      OUT_POLARITY_G  : boolean                          := true;
       BYPASS_SYNC_G   : boolean                          := false;  -- Bypass Synchronizer module for synchronous data configuration
       RELEASE_DELAY_G : integer range 3 to positive'high := 3;  -- Delay between deassertion of async and sync resets
       OUT_REG_RST_G   : boolean                          := true);  -- Apply async reset to final reg stage
@@ -35,7 +35,7 @@ end RstSync;
 
 architecture rtl of RstSync is
 
-   signal syncInt : sl := OUT_POLARITY_G;
+   signal syncInt : sl := toSl(OUT_POLARITY_G);
 
 begin
 
@@ -49,18 +49,18 @@ begin
          RST_ASYNC_G    => true,
          STAGES_G       => RELEASE_DELAY_G-1,
          BYPASS_SYNC_G  => BYPASS_SYNC_G,
-         INIT_G         => slvAll(RELEASE_DELAY_G-1, OUT_POLARITY_G))
+         INIT_G         => slvAll(RELEASE_DELAY_G-1, toSl(OUT_POLARITY_G)))
       port map (
          clk     => clk,
          rst     => asyncRst,
-         dataIn  => not OUT_POLARITY_G,
+         dataIn  => not toSl(OUT_POLARITY_G),
          dataOut => syncInt);
 
    -- Final stage does not have async constraints applied, can be duplicated to ease timing
    OUT_REG : process (clk, asyncRst) is
    begin
-      if (asyncRst = IN_POLARITY_G and OUT_REG_RST_G) then
-         syncRst <= OUT_POLARITY_G after TPD_G;
+      if (asyncRst = toSl(IN_POLARITY_G) and OUT_REG_RST_G) then
+         syncRst <= toSl(OUT_POLARITY_G) after TPD_G;
       elsif (rising_edge(clk)) then
          syncRst <= syncInt after TPD_G;
       end if;

base/sync/rtl/Synchronizer.vhd

@@ -22,17 +22,17 @@ use surf.StdRtlPkg.all;
 entity Synchronizer is
    generic (
       TPD_G          : time     := 1 ns;
-      RST_POLARITY_G : sl       := '1';    -- '1' for active HIGH reset, '0' for active LOW reset
-      OUT_POLARITY_G : sl       := '1';    -- 0 for active LOW, 1 for active HIGH
+      RST_POLARITY_G : boolean  := true;   -- true for active HIGH reset, false for active LOW reset
+      OUT_POLARITY_G : boolean  := true;   -- false for active LOW, true for active HIGH
       RST_ASYNC_G    : boolean  := false;  -- Reset is asynchronous
       STAGES_G       : positive := 2;
       BYPASS_SYNC_G  : boolean  := false;  -- Bypass Synchronizer module for synchronous data configuration
       INIT_G         : slv      := "0");
    port (
-      clk     : in  sl;                 -- clock to be SYNC'd to
-      rst     : in  sl := not RST_POLARITY_G;  -- Optional reset
-      dataIn  : in  sl;                 -- Data to be 'synced'
-      dataOut : out sl);                -- synced data
+      clk     : in  sl;                              -- clock to be SYNC'd to
+      rst     : in  sl := not toSl(RST_POLARITY_G);  -- Optional reset
+      dataIn  : in  sl;                              -- Data to be 'synced'
+      dataOut : out sl);                             -- synced data
 end Synchronizer;
 
 architecture rtl of Synchronizer is
@@ -83,7 +83,7 @@ begin
       begin
          rin <= crossDomainSyncReg(STAGES_G-2 downto 0) & dataIn;
 
-         if (OUT_POLARITY_G = '1') then
+         if (OUT_POLARITY_G) then
             dataOut <= crossDomainSyncReg(STAGES_G-1);
          else
             dataOut <= not(crossDomainSyncReg(STAGES_G-1));
@@ -97,7 +97,7 @@ begin
             if (rising_edge(clk)) then
                crossDomainSyncReg <= rin after TPD_G;
             end if;
-            if (rst = RST_POLARITY_G) then
+            if (rst = toSl(RST_POLARITY_G)) then
                crossDomainSyncReg <= INIT_C after TPD_G;
             end if;
          end process seq;
@@ -107,7 +107,7 @@ begin
          seq : process (clk) is
          begin
             if (rising_edge(clk)) then
-               if (rst = RST_POLARITY_G) then
+               if (rst = toSl(RST_POLARITY_G)) then
                   crossDomainSyncReg <= INIT_C after TPD_G;
                else
                   crossDomainSyncReg <= rin after TPD_G;
@@ -120,7 +120,7 @@ begin
 
    BYPASS : if (BYPASS_SYNC_G = true) generate
 
-      dataOut <= dataIn when(OUT_POLARITY_G = '1') else not(dataIn);
+      dataOut <= dataIn when(OUT_POLARITY_G) else not(dataIn);
 
    end generate;
 

base/sync/rtl/SynchronizerEdge.vhd

@@ -21,19 +21,19 @@ use surf.StdRtlPkg.all;
 entity SynchronizerEdge is
    generic (
       TPD_G          : time     := 1 ns;
-      RST_POLARITY_G : sl       := '1';    -- '1' for active HIGH reset, '0' for active LOW reset
-      OUT_POLARITY_G : sl       := '1';    -- 0 for active LOW, 1 for active HIGH
+      RST_POLARITY_G : boolean  := true;   -- true for active HIGH reset, false for active LOW reset
+      OUT_POLARITY_G : boolean  := true;   -- false for active LOW, true for active HIGH
       RST_ASYNC_G    : boolean  := false;  -- Reset is asynchronous
       BYPASS_SYNC_G  : boolean  := false;  -- Bypass Synchronizer module for synchronous data configuration
       STAGES_G       : positive := 3;
       INIT_G         : slv      := "0");
    port (
-      clk         : in  sl;                        -- clock to be SYNC'd to
-      rst         : in  sl := not RST_POLARITY_G;  -- Optional reset
-      dataIn      : in  sl;                        -- Data to be 'synced'
-      dataOut     : out sl;                        -- synced data
-      risingEdge  : out sl;                        -- Rising edge detected
-      fallingEdge : out sl);                       -- Falling edge detected
+      clk         : in  sl;                              -- clock to be SYNC'd to
+      rst         : in  sl := not toSl(RST_POLARITY_G);  -- Optional reset
+      dataIn      : in  sl;                              -- Data to be 'synced'
+      dataOut     : out sl;                              -- synced data
+      risingEdge  : out sl;                              -- Rising edge detected
+      fallingEdge : out sl);                             -- Falling edge detected
 end SynchronizerEdge;
 
 architecture rtl of SynchronizerEdge is
@@ -48,9 +48,9 @@ architecture rtl of SynchronizerEdge is
    end record RegType;
    constant REG_INIT_C : RegType := (
       syncDataDly => '0',
-      dataOut     => (not OUT_POLARITY_G),
-      risingEdge  => (not OUT_POLARITY_G),
-      fallingEdge => (not OUT_POLARITY_G));
+      dataOut     => (not toSl(OUT_POLARITY_G)),
+      risingEdge  => (not toSl(OUT_POLARITY_G)),
+      fallingEdge => (not toSl(OUT_POLARITY_G)));
 
    signal r   : RegType := REG_INIT_C;
    signal rin : RegType;
@@ -65,7 +65,7 @@ begin
       generic map (
          TPD_G          => TPD_G,
          RST_POLARITY_G => RST_POLARITY_G,
-         OUT_POLARITY_G => '1',
+         OUT_POLARITY_G => true,
          RST_ASYNC_G    => RST_ASYNC_G,
          STAGES_G       => (STAGES_G-1),
          BYPASS_SYNC_G  => BYPASS_SYNC_G,
@@ -83,31 +83,31 @@ begin
       v := r;
 
       -- Reset strobe signals
-      v.risingEdge  := not OUT_POLARITY_G;
-      v.fallingEdge := not OUT_POLARITY_G;
+      v.risingEdge  := not toSl(OUT_POLARITY_G);
+      v.fallingEdge := not toSl(OUT_POLARITY_G);
 
       -- Keep a record of the last syncData
       v.syncDataDly := syncData;
 
       -- Set the polarity of the output
-      if (OUT_POLARITY_G = '1') then
+      if (OUT_POLARITY_G) then
          v.dataOut := syncData;
       else
          v.dataOut := not(syncData);
       end if;
 
       -- Check for a rising edge of the syncData
       if (syncData = '1') and (r.syncDataDly = '0') then
-         v.risingEdge := OUT_POLARITY_G;
+         v.risingEdge := toSl(OUT_POLARITY_G);
       end if;
 
       -- Check for a rising edge of the syncData
       if (syncData = '0') and (r.syncDataDly = '1') then
-         v.fallingEdge := OUT_POLARITY_G;
+         v.fallingEdge := toSl(OUT_POLARITY_G);
       end if;
 
       -- Sync Reset
-      if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
+      if (RST_ASYNC_G = false and rst = toSl(RST_POLARITY_G)) then
          v             := REG_INIT_C;
          v.syncDataDly := syncData;     -- prevent accidental edge detection
       end if;
@@ -128,7 +128,7 @@ begin
          r <= rin after TPD_G;
       end if;
       -- Async Reset
-      if (RST_ASYNC_G and rst = RST_POLARITY_G) then
+      if (RST_ASYNC_G and rst = toSl(RST_POLARITY_G)) then
          r             <= REG_INIT_C after TPD_G;
          r.syncDataDly <= syncData   after TPD_G;  -- prevent accidental edge detection
       end if;