depreciating VLAN support in ethernet/EthMacCore because never tested…

… and never used
slaclab · Jul 11, 2024 · 9c6aee9 · 9c6aee9
1 parent 15a7282
commit 9c6aee9
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Showing 10 changed files with 314 additions and 880 deletions.
diff --git a/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd b/ethernet/EthMacCore/rtl/EthMacFlowCtrl.vhd
@@ -17,25 +17,21 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiStreamPkg.all;
 
 entity EthMacFlowCtrl is
    generic (
-      TPD_G       : time                  := 1 ns;
-      BYP_EN_G    : boolean               := false;
-      VLAN_EN_G   : boolean               := false;
-      VLAN_SIZE_G : positive range 1 to 8 := 1);
+      TPD_G    : time    := 1 ns;
+      BYP_EN_G : boolean := false);
    port (
       -- Clock and Reset
       ethClk   : in  sl;
       ethRst   : in  sl;
       -- Inputs
       primCtrl : in  AxiStreamCtrlType;
       bypCtrl  : in  AxiStreamCtrlType;
-      vlanCtrl : in  AxiStreamCtrlArray(VLAN_SIZE_G-1 downto 0);
       -- Output
       flowCtrl : out AxiStreamCtrlType);
 end EthMacFlowCtrl;
@@ -56,7 +52,7 @@ architecture rtl of EthMacFlowCtrl is
 
 begin
 
-   comb : process (bypCtrl, ethRst, primCtrl, r, vlanCtrl) is
+   comb : process (bypCtrl, ethRst, primCtrl, r) is
       variable v : RegType;
       variable i : natural;
    begin
@@ -80,21 +76,6 @@ begin
          end if;
       end if;
 
-      -- Check if VLAN interface is enabled
-      if (VLAN_EN_G) then
-         -- Loop through the channels
-         for i in (VLAN_SIZE_G-1) downto 0 loop
-            -- Sample the VLAN pause
-            if (vlanCtrl(i).pause = '1') then
-               v.flowCtrl.pause := '1';
-            end if;
-            -- Sample the VLAN overflow
-            if (vlanCtrl(i).overflow = '1') then
-               v.flowCtrl.overflow := '1';
-            end if;
-         end loop;
-      end if;
-
       -- Reset
       if (ethRst = '1') then
          v := REG_INIT_C;

diff --git a/ethernet/EthMacCore/rtl/EthMacRx.vhd b/ethernet/EthMacCore/rtl/EthMacRx.vhd
@@ -17,7 +17,6 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-
 library surf;
 use surf.AxiStreamPkg.all;
 use surf.StdRtlPkg.all;
@@ -26,21 +25,17 @@ use surf.EthMacPkg.all;
 entity EthMacRx is
    generic (
       -- Simulation Generics
-      TPD_G          : time                  := 1 ns;
+      TPD_G          : time             := 1 ns;
       -- MAC Configurations
-      PAUSE_EN_G     : boolean               := true;
-      PHY_TYPE_G     : string                := "XGMII";
-      JUMBO_G        : boolean               := true;
-      -- Non-VLAN Configurations
-      FILT_EN_G      : boolean               := false;
-      BYP_EN_G       : boolean               := false;
-      BYP_ETH_TYPE_G : slv(15 downto 0)      := x"0000";
-      -- VLAN Configurations
-      VLAN_EN_G      : boolean               := false;
-      VLAN_SIZE_G    : positive range 1 to 8 := 1;
-      VLAN_VID_G     : Slv12Array            := (0 => x"001");
-      -- Internal RAM sythesis mode
-      SYNTH_MODE_G   : string                := "inferred");
+      PAUSE_EN_G     : boolean          := true;
+      PHY_TYPE_G     : string           := "XGMII";
+      JUMBO_G        : boolean          := true;
+      -- Misc. Configurations
+      FILT_EN_G      : boolean          := false;
+      BYP_EN_G       : boolean          := false;
+      BYP_ETH_TYPE_G : slv(15 downto 0) := x"0000";
+      -- Internal RAM synthesis mode
+      SYNTH_MODE_G   : string           := "inferred");
    port (
       -- Clock and Reset
       ethClkEn     : in  sl;
@@ -52,9 +47,6 @@ entity EthMacRx is
       -- Bypass Interface
       mBypMaster   : out AxiStreamMasterType;
       mBypCtrl     : in  AxiStreamCtrlType;
-      -- VLAN Interfaces
-      mVlanMasters : out AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0);
-      mVlanCtrl    : in  AxiStreamCtrlArray(VLAN_SIZE_G-1 downto 0);
       -- XLGMII PHY Interface
       xlgmiiRxd    : in  slv(127 downto 0);
       xlgmiiRxc    : in  slv(15 downto 0);
@@ -79,7 +71,6 @@ architecture mapping of EthMacRx is
 
    signal macIbMaster  : AxiStreamMasterType;
    signal pauseMaster  : AxiStreamMasterType;
-   signal pauseMasters : AxiStreamMasterArray(VLAN_SIZE_G-1 downto 0);
    signal csumMaster   : AxiStreamMasterType;
    signal bypassMaster : AxiStreamMasterType;
 
@@ -120,11 +111,8 @@ begin
    ------------------
    U_Pause : entity surf.EthMacRxPause
       generic map (
-         TPD_G       => TPD_G,
-         PAUSE_EN_G  => PAUSE_EN_G,
-         VLAN_EN_G   => VLAN_EN_G,
-         VLAN_SIZE_G => VLAN_SIZE_G,
-         VLAN_VID_G  => VLAN_VID_G)
+         TPD_G      => TPD_G,
+         PAUSE_EN_G => PAUSE_EN_G)
       port map (
          -- Clock and Reset
          ethClk       => ethClk,
@@ -133,19 +121,17 @@ begin
          sAxisMaster  => macIbMaster,
          -- Outgoing data
          mAxisMaster  => pauseMaster,
-         mAxisMasters => pauseMasters,
          -- Pause Values
          rxPauseReq   => rxPauseReq,
          rxPauseValue => rxPauseValue);
 
-   ------------------------------
-   -- RX Non-VLAN Checksum Module
-   ------------------------------
+   ---------------------
+   -- RX Checksum Module
+   ---------------------
    U_Csum : entity surf.EthMacRxCsum
       generic map (
          TPD_G   => TPD_G,
-         JUMBO_G => JUMBO_G,
-         VLAN_G  => false)
+         JUMBO_G => JUMBO_G)
       port map (
          -- Clock and Reset
          ethClk      => ethClk,
@@ -158,36 +144,6 @@ begin
          sAxisMaster => pauseMaster,
          mAxisMaster => csumMaster);
 
-   --------------------------
-   -- RX VLAN Checksum Module
-   --------------------------
-   GEN_VLAN : if (VLAN_EN_G = true) generate
-      GEN_VEC :
-      for i in (VLAN_SIZE_G-1) downto 0 generate
-         U_Csum : entity surf.EthMacRxCsum
-            generic map (
-               TPD_G   => TPD_G,
-               JUMBO_G => JUMBO_G,
-               VLAN_G  => true)
-            port map (
-               -- Clock and Reset
-               ethClk      => ethClk,
-               ethRst      => ethRst,
-               -- Configurations
-               ipCsumEn    => '1',
-               tcpCsumEn   => '1',
-               udpCsumEn   => '1',
-               -- Outbound data to MAC
-               sAxisMaster => pauseMasters(i),
-               mAxisMaster => mVlanMasters(i));
-      end generate GEN_VEC;
-   end generate;
-
-   BYPASS_VLAN : if (VLAN_EN_G = false) generate
-      -- Terminate Unused buses
-      mVlanMasters <= (others => AXI_STREAM_MASTER_INIT_C);
-   end generate;
-
    -------------------
    -- RX Bypass Module
    -------------------