bug fix when using ultrascale+ FPGAs

slaclab · Jul 11, 2024 · a6012a4 · a6012a4
1 parent 766081b
commit a6012a4
Showing 1 changed file with 8 additions and 4 deletions.
diff --git a/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd b/protocols/xvc-udp/rtl/UdpDebugBridgeWrapper.vhd
@@ -42,8 +42,8 @@ end UdpDebugBridgeWrapper;
 architecture rtl of UdpDebugBridgeWrapper is
 
    component UdpDebugBridge is
-      generic (
-         AXIS_CLK_FREQ_G : real);
+--      generic (
+--         AXIS_CLK_FREQ_G : real);
       port (
          axisClk            : in  std_logic;
          axisRst            : in  std_logic;
@@ -81,6 +81,10 @@ architecture rtl of UdpDebugBridgeWrapper is
 
 begin
 
+   assert (AXIS_CLK_FREQ_G = 156.25E+6)
+      report "AXIS_CLK_FREQ_G: Must be 156.25E+6"
+      severity error;
+
    ----------------------------
    -- 'XVC' Server @2542 (modified protocol to work over UDP)
    ----------------------------
@@ -115,8 +119,8 @@ begin
    end process P_SOF_SPLICE;
 
    U_XvcServer : component UdpDebugBridge
-      generic map (
-         AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G)
+--      generic map (
+--         AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G)
       port map (
          axisClk => clk,
          axisRst => rst,