Merge pull request #1200 from slaclab/Pgp4RxLiteLowSpeedLane

Pgp4RxLiteLowSpeedLane.vhd Update
slaclab · Sep 30, 2024 · ea63530 · ea63530
2 parents 5008bb0 + 75e91c1
commit ea63530
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4RxLiteLowSpeedLane.vhd
@@ -30,7 +30,7 @@ entity Pgp4RxLiteLowSpeedLane is
       DLY_STEP_SIZE_G    : positive range 1 to 255 := 1;
       STATUS_CNT_WIDTH_G : natural range 1 to 32   := 16;
       ERROR_CNT_WIDTH_G  : natural range 1 to 32   := 8;
-      AXIL_CLK_FREQ_G    : real); -- In units of HZ
+      AXIL_CLK_FREQ_G    : real);       -- In units of HZ
    port (
       -- Deserialization Interface (deserClk domain)
       deserClk        : in  sl;
@@ -72,6 +72,8 @@ architecture mapping of Pgp4RxLiteLowSpeedLane is
    signal phyRxValid : sl := '0';
    signal phyRxData  : slv(65 downto 0);
 
+   signal phyRxValidMask : sl := '0';
+
 begin
 
    process(deserClk)
@@ -151,6 +153,9 @@ begin
          eyeWidth        => eyeWidth,
          locked          => gearboxAligned);
 
+   -- Mask off the Valid until the gearbox is locked
+   phyRxValidMask <= phyRxValid and gearboxAligned;
+
    ------------------
    -- PGPv4 Core Lite
    ------------------
@@ -186,7 +191,7 @@ begin
          phyRxRst        => deserReset,
          phyRxActive     => gearboxAligned,
          phyRxStartSeq   => '0',
-         phyRxValid      => phyRxValid,
+         phyRxValid      => phyRxValidMask,
          phyRxData       => phyRxData(63 downto 0),
          phyRxHeader     => phyRxData(65 downto 64),
          -- AXI-Lite Register Interface (axilClk domain)