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adding frameCnt register to SsiPrbsRx & SsiPrbsTx #1155

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merged 7 commits into from
Apr 26, 2024
Merged

adding frameCnt register to SsiPrbsRx & SsiPrbsTx #1155

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9a06f76
adding frameCnt register to SsiPrbsRx.vhd
ruck314 Apr 26, 2024
3fdba6e
adding frameCnt register to _SsiPrbsRx.py
ruck314 Apr 26, 2024
7f4f7ec
whitespace removal
ruck314 Apr 26, 2024
ebe0633
adding frameCnt register to SsiPrbsTx.vhd
ruck314 Apr 26, 2024
8458fdc
adding frameCnt register to _SsiPrbsTx.py
ruck314 Apr 26, 2024
6d97ff2
adding PRBS_SEED_SIZE_G missing register
ruck314 Apr 26, 2024
b965d64
bug fix
ruck314 Apr 26, 2024
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2 changes: 1 addition & 1 deletion protocols/i2c/rtl/I2cRegMaster.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -209,7 +209,7 @@ begin
v.i2cMasterIn.txnReq := '1';
v.i2cMasterIn.op := '0';
v.i2cMasterIn.stop := '1'; -- i2c stop after all bytes are read
v.byteCount := (others => '0');
v.byteCount := (others => '0');
v.state := READ_S;

when READ_S =>
Expand Down
62 changes: 34 additions & 28 deletions protocols/ssi/rtl/SsiPrbsRx.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -158,7 +158,7 @@ architecture rtl of SsiPrbsRx is

signal axisCtrl : AxiStreamCtrlArray(1 downto 0) := (others => AXI_STREAM_CTRL_UNUSED_C);

constant STATUS_SIZE_C : positive := 10;
constant STATUS_SIZE_C : positive := 11;

type LocRegType is record
cntRst : sl;
Expand All @@ -180,6 +180,7 @@ architecture rtl of SsiPrbsRx is
signal rAxiLite : LocRegType := LOC_REG_INIT_C;
signal rinAxiLite : LocRegType;

signal updatedResultsSync : sl;
signal errBitStrbSync : sl;
signal errWordStrbSync : sl;
signal errDataBusSync : sl;
Expand All @@ -196,6 +197,7 @@ architecture rtl of SsiPrbsRx is
signal packetRateSync : slv(31 downto 0);
signal errWordCntSync : slv(31 downto 0);

signal frameCnt : slv(STATUS_CNT_WIDTH_G-1 downto 0);
signal pause1Cnt : slv(STATUS_CNT_WIDTH_G-1 downto 0);
signal overflow1Cnt : slv(STATUS_CNT_WIDTH_G-1 downto 0);
signal pause0Cnt : slv(STATUS_CNT_WIDTH_G-1 downto 0);
Expand Down Expand Up @@ -551,35 +553,38 @@ begin
WIDTH_G => STATUS_SIZE_C)
port map (
-- Input Status bit Signals (wrClk domain)
statusIn(9) => axisCtrl(1).pause,
statusIn(8) => axisCtrl(1).overflow,
statusIn(7) => axisCtrl(0).pause,
statusIn(6) => axisCtrl(0).overflow,
statusIn(5) => '0', -- Legacy
statusIn(4) => r.errWordStrb,
statusIn(3) => r.errDataBus,
statusIn(2) => r.eofe,
statusIn(1) => r.errLength,
statusIn(0) => r.errMissedPacket,
statusIn(10) => r.updatedResults,
statusIn(9) => axisCtrl(1).pause,
statusIn(8) => axisCtrl(1).overflow,
statusIn(7) => axisCtrl(0).pause,
statusIn(6) => axisCtrl(0).overflow,
statusIn(5) => '0', -- Legacy
statusIn(4) => r.errWordStrb,
statusIn(3) => r.errDataBus,
statusIn(2) => r.eofe,
statusIn(1) => r.errLength,
statusIn(0) => r.errMissedPacket,
-- Output Status bit Signals (rdClk domain)
statusOut(9) => pause(1),
statusOut(8) => overflow(1),
statusOut(7) => pause(0),
statusOut(6) => overflow(0),
statusOut(5) => errBitStrbSync,
statusOut(4) => errWordStrbSync,
statusOut(3) => errDataBusSync,
statusOut(2) => errEofeSync,
statusOut(1) => errLengthSync,
statusOut(0) => errMissedPacketSync,
statusOut(10) => updatedResultsSync,
statusOut(9) => pause(1),
statusOut(8) => overflow(1),
statusOut(7) => pause(0),
statusOut(6) => overflow(0),
statusOut(5) => errBitStrbSync,
statusOut(4) => errWordStrbSync,
statusOut(3) => errDataBusSync,
statusOut(2) => errEofeSync,
statusOut(1) => errLengthSync,
statusOut(0) => errMissedPacketSync,
-- Status Bit Counters Signals (rdClk domain)
cntRstIn => rAxiLite.cntRst,
rollOverEnIn => rAxiLite.rollOverEn,
cntOut => cntOut,
cntRstIn => rAxiLite.cntRst,
rollOverEnIn => rAxiLite.rollOverEn,
cntOut => cntOut,
-- Clocks and Reset Ports
wrClk => sAxisClk,
rdClk => axiClk);
wrClk => sAxisClk,
rdClk => axiClk);

frameCnt <= muxSlVectorArray(cntOut, 10);
pause1Cnt <= muxSlVectorArray(cntOut, 9);
overflow1Cnt <= muxSlVectorArray(cntOut, 8);
pause0Cnt <= muxSlVectorArray(cntOut, 7);
Expand All @@ -598,7 +603,7 @@ begin
errDataBusSync, errEofeCnt, errEofeSync,
errLengthCnt, errLengthSync, errMissedPacketCnt,
errMissedPacketSync, errWordCntSync, errWordStrbCnt,
errWordStrbSync, overflow, overflow0Cnt,
errWordStrbSync, frameCnt, overflow, overflow0Cnt,
overflow1Cnt, packetLengthSync, packetRateSync,
pause, pause0Cnt, pause1Cnt, rAxiLite) is
variable v : LocRegType;
Expand Down Expand Up @@ -629,7 +634,7 @@ begin
axiSlaveRegisterR(axilEp, X"70", 2, errEofeSync);
axiSlaveRegisterR(axilEp, X"70", 3, errDataBusSync);
axiSlaveRegisterR(axilEp, X"70", 4, errWordStrbSync);
axiSlaveRegisterR(axilEp, X"70", 5, '0'); -- legacy errBitStrbSync
axiSlaveRegisterR(axilEp, X"70", 5, '0'); -- legacy errBitStrbSync
axiSlaveRegisterR(axilEp, X"70", 6, overflow(0));
axiSlaveRegisterR(axilEp, X"70", 7, pause(0));
axiSlaveRegisterR(axilEp, X"70", 8, overflow(1));
Expand All @@ -638,6 +643,7 @@ begin
axiSlaveRegisterR(axilEp, X"78", 0, packetRateSync);
axiSlaveRegisterR(axilEp, X"7C", 0, X"00000000"); -- legacy errBitCntSync
axiSlaveRegisterR(axilEp, X"80", 0, errWordCntSync);
axiSlaveRegisterR(axilEp, X"84", 0, frameCnt);
axiSlaveRegister(axilEp, X"F0", 0, v.rollOverEn);
axiSlaveRegister(axilEp, X"F4", 0, v.bypCheck);
axiSlaveRegisterR(axilEp, X"F8", 0, toSlv(PRBS_SEED_SIZE_G, 32));
Expand Down
17 changes: 17 additions & 0 deletions protocols/ssi/rtl/SsiPrbsTx.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -93,8 +93,10 @@ architecture rtl of SsiPrbsTx is
DATA_S);

type RegType is record
cntRst : sl;
busy : sl;
overflow : sl;
frameCnt : slv(31 downto 0);
length : slv(31 downto 0);
packetLength : slv(31 downto 0);
dataCnt : slv(31 downto 0);
Expand All @@ -116,8 +118,10 @@ architecture rtl of SsiPrbsTx is
end record;

constant REG_INIT_C : RegType := (
cntRst => '1',
busy => '1',
overflow => '0',
frameCnt => (others => '0'),
length => (others => '0'),
packetLength => AXI_DEFAULT_PKT_LEN_G,
dataCnt => (others => '0'),
Expand Down Expand Up @@ -155,6 +159,9 @@ begin
-- Latch the current value
v := r;

-- Reset strobes
v.cntRst := '0';

----------------------------------------------------------------------------------------------
-- Axi-Lite Registers
----------------------------------------------------------------------------------------------
Expand All @@ -178,6 +185,9 @@ begin
axiSlaveRegisterR(axilEp, X"1C", 0, r.trigDly);

axiSlaveRegisterR(axilEp, X"20", 0, toSlv(PRBS_SEED_SIZE_G, 32));
axiSlaveRegisterR(axilEp, X"24", 0, r.frameCnt);

axiWrDetect(axilEp, X"FC", v.cntRst);

axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C);

Expand Down Expand Up @@ -266,6 +276,8 @@ begin
v.dataCnt := r.dataCnt + 1;
-- Set the SOF bit
ssiSetUserSof(PRBS_SSI_CONFIG_C, v.txAxisMaster, '1');
-- Count the frame
v.frameCnt := r.frameCnt + 1;
-- Next State
v.state := LENGTH_S;
end if;
Expand Down Expand Up @@ -320,6 +332,11 @@ begin
----------------------------------------------------------------------
end case;

-- Check for counter reset
if (r.cntRst = '1') then
v.frameCnt := (others=>'0');
end if;

-- Reset
if (RST_ASYNC_G = false and locRst = '1') then
v := REG_INIT_C;
Expand Down
9 changes: 9 additions & 0 deletions python/surf/protocols/ssi/_SsiPrbsRx.py
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Original file line number Diff line number Diff line change
Expand Up @@ -195,6 +195,15 @@ def __init__(self,
pollInterval = 1,
))

self.add(pr.RemoteVariable(
name = "FrameCnt",
description = "",
offset = 0x84,
bitSize = 32,
mode = "RO",
pollInterval = 1,
))

self.add(pr.RemoteVariable(
name = "RolloverEnable",
description = "",
Expand Down
20 changes: 20 additions & 0 deletions python/surf/protocols/ssi/_SsiPrbsTx.py
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