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Create SaciAxiLiteMaster module #1163

Merged
merged 23 commits into from
Sep 6, 2024
Merged

Create SaciAxiLiteMaster module #1163

merged 23 commits into from
Sep 6, 2024

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bengineerd
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@bengineerd bengineerd commented Jun 11, 2024

Description

Add a new SaciAxiLiteMaster module. This module is intended to be paired with AxiLiteSaciMaster. Together they create a an AXI-Lite bridge between two chips carried over the SACI bus.

Details

Only 20 bits of AXI-Lite address space are available, due to the limited address bits on the SACI bus protocol.

Also added a cocotb testbench for the new module.

@bengineerd bengineerd changed the base branch from master to pre-release June 11, 2024 05:29
@bengineerd bengineerd marked this pull request as ready for review September 6, 2024 04:34
@ruck314 ruck314 merged commit 7b4c2d9 into pre-release Sep 6, 2024
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@ruck314 ruck314 deleted the SaciAxiLiteMaster branch September 6, 2024 14:31
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2 participants