Bug Fixes and Enhancements from LDMX Project Development

[bengineerd]

Description

There are many small changes, mostly to fix issues found in simulation.

Details

• AxiStreamResize
  • Better error reporting if generic assert fails
• Ad9249ReadoutGroup2
  • Initialize signal to avoid unknowns in simulation
• Ad9249Group (simulation)
  • Fix incomplete sensitivity list
• Pgp2FcAxi
  • Apply TX FC bus from input to PGP block
• PGP2FC GTY IP Core
  • Remove "project_parameters" from XCI file
  • Allows XCI to load with different US+ FPGAs
• PGP2FC GTY IP Core Wrapper
  • Output rxPmaResetDone
    • Needed for external MMCM reset
  • Update resets based on simulation discoveries
  • Set freerun frequency to 185.71/2 MHz
• Add GTH IP Core and wrapper for PGP2FC
• ClockManagerUltraScale (Plus)
  • Resolve unknowns on DrpDo output from GT to zeros to avoid propagating them in simulation
• GtRxAlignCheck
  • Use registered values for read-only AXI-Lite registers
  • Apply bug fix so resetErr only reset the FSM when resetDone is high
• Rogue Devices
  • Add several registers to the "NoConfig" group