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Update DmaXvcWrapper.vhd #1177

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merged 3 commits into from
Jul 11, 2024
Merged

Update DmaXvcWrapper.vhd #1177

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74c8236
Update DmaXvcWrapper.vhd's generic from AXIS_CLK_FREQ_G to XVC_CLK_FR…
ruck314 Jul 11, 2024
766081b
cleaning up DmaXvcWrapper interfaces and confirmed it works with Simp…
ruck314 Jul 11, 2024
a6012a4
bug fix when using ultrascale+ FPGAs
ruck314 Jul 11, 2024
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4 changes: 2 additions & 2 deletions protocols/xvc-udp/rtl/DmaXvcWrapper.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ entity DmaXvcWrapper is
generic (
TPD_G : time := 1 ns;
COMMON_CLOCK_G : boolean := false;
AXIS_CLK_FREQ_G : real := 156.25e6;
XVC_CLK_FREQ_G : real := 156.25e6;
FIFO_INT_PIPE_STAGES_G : natural range 0 to 16 := 0; -- Internal FIFO setting
FIFO_PIPE_STAGES_G : natural range 0 to 16 := 1;
OB_FIFO_SLAVE_READY_EN_G : boolean := true;
Expand Down Expand Up @@ -67,7 +67,7 @@ begin
U_XVC : entity surf.UdpDebugBridgeWrapper
generic map (
TPD_G => TPD_G,
AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G)
AXIS_CLK_FREQ_G => XVC_CLK_FREQ_G)
port map (
-- Clock and Reset
clk => xvcClk,
Expand Down
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