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Release Candidate v2.51.0 #1196

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merged 26 commits into from
Oct 2, 2024
Merged

Release Candidate v2.51.0 #1196

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5106757
adding userCLk to SelectioDeserUltraScale.vhd
ruck314 Sep 20, 2024
498884a
adding Pgp4RxLiteLowSpeed.vhd
ruck314 Sep 23, 2024
9e5df72
Merge pull request #1194 from slaclab/ruckman/SelectioDeserUltraScale
ruck314 Sep 23, 2024
572db27
Increased range of SACI_NUM_CHIPS_G from 4 to 6.
hsandber Sep 24, 2024
eddb613
Update RstSync.vhd
ruck314 Sep 25, 2024
062d3b1
Merge pull request #1198 from slaclab/RstSync-std_logic
ruck314 Sep 25, 2024
e972e75
remove AXIL_CLK_FREQ_G default to force user to define it
ruck314 Sep 26, 2024
c6b9e8b
remove AXIL_CLK_FREQ_G default to force user to define it
ruck314 Sep 26, 2024
63d5f22
Merge pull request #1195 from slaclab/Pgp4RxLiteLowSpeed
ruck314 Sep 26, 2024
1ed83db
adding support to run SACI clock when asicRstL asserted in SACI_CLK_F…
ruck314 Sep 26, 2024
5008bb0
Merge pull request #1199 from slaclab/AxiLiteSaciMaster-asicRstL-aware
ruck314 Sep 27, 2024
75e91c1
Pgp4RxLiteLowSpeedLane.vhd Update
ruck314 Sep 28, 2024
ea63530
Merge pull request #1200 from slaclab/Pgp4RxLiteLowSpeedLane
ruck314 Sep 30, 2024
b429843
Removing upper bound from range
ruck314 Oct 1, 2024
de4825d
Merge pull request #1197 from slaclab/saci_6_chip
ruck314 Oct 1, 2024
3ea9a75
adding TxDisable to _Qsfp.py
ruck314 Oct 1, 2024
56ad103
adding PowerOverride & PowerMode registers
ruck314 Oct 1, 2024
2bff33d
introduce rst_polarity feature to all pgp4txlite/pgp4rx modules to pr…
cbakalis-slac Oct 1, 2024
3c04de5
remove defaults on rst input ports; purge SIMULATION_G from Pgp4Rx.vhd
cbakalis-slac Oct 1, 2024
ba2710e
bug fix for existing builds
ruck314 Oct 2, 2024
000e2e6
Merge pull request #1204 from slaclab/pgp4lite-rstPolarity
ruck314 Oct 2, 2024
6d5bba6
restoring default on crcPwrOnRst after PR#1204
ruck314 Oct 2, 2024
03e838e
restoring default on crcPwrOnRst after PR#1204
ruck314 Oct 2, 2024
8f30131
Fixed typo
ruck314 Oct 2, 2024
9250912
Merge pull request #1203 from slaclab/Qsfp-TxDisable
ruck314 Oct 2, 2024
5238204
./emacs -f vhdl-beautify-buffer -f vhdl-update-sensitivity-list-buffe…
ruck314 Oct 2, 2024
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17 changes: 9 additions & 8 deletions axi/axi-stream/rtl/AxiStreamDeMux.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@ use surf.AxiStreamPkg.all;
entity AxiStreamDeMux is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
NUM_MASTERS_G : integer range 1 to 256 := 12;
MODE_G : string := "INDEXED"; -- Or "ROUTED" Or "DYNAMIC"
Expand All @@ -39,7 +40,7 @@ entity AxiStreamDeMux is
axisRst : in sl;
-- Dynamic Route Table (only used when MODE_G = "DYNAMIC")
dynamicRouteMasks : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
-- Slave
sAxisMaster : in AxiStreamMasterType;
sAxisSlave : out AxiStreamSlaveType;
Expand Down Expand Up @@ -139,7 +140,7 @@ begin
sAxisSlave <= v.slave;

-- Reset
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -151,14 +152,14 @@ begin

end process comb;

GEN_VEC :
for i in (NUM_MASTERS_G-1) downto 0 generate
GEN_VEC : for i in (NUM_MASTERS_G-1) downto 0 generate

U_Pipeline : entity surf.AxiStreamPipeline
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
port map (
axisClk => axisClk,
axisRst => axisRst,
Expand All @@ -171,7 +172,7 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G and axisRst = '1') then
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axisClk) then
r <= rin after TPD_G;
Expand Down
12 changes: 7 additions & 5 deletions axi/axi-stream/rtl/AxiStreamMux.vhd
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Expand Up @@ -27,6 +27,7 @@ use surf.AxiStreamPkg.all;
entity AxiStreamMux is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
PIPE_STAGES_G : integer range 0 to 16 := 0;
NUM_SLAVES_G : integer range 1 to 256 := 4;
Expand Down Expand Up @@ -308,7 +309,7 @@ begin
sAxisSlaves <= v.slaves;

-- Reset
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -322,7 +323,7 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G) and (axisRst = '1') then
if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axisClk) then
r <= rin after TPD_G;
Expand All @@ -332,9 +333,10 @@ begin
-- Optional output pipeline registers to ease timing
AxiStreamPipeline_1 : entity surf.AxiStreamPipeline
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => PIPE_STAGES_G)
port map (
axisClk => axisClk,
axisRst => axisRst,
Expand Down
5 changes: 3 additions & 2 deletions axi/axi-stream/rtl/AxiStreamPipeline.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ use surf.AxiStreamPkg.all;
entity AxiStreamPipeline is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
SIDE_BAND_WIDTH_G : positive := 1; -- General purpose sideband
PIPE_STAGES_G : natural := 0);
Expand Down Expand Up @@ -148,7 +149,7 @@ begin
mSideBand <= r.mSideBand(PIPE_STAGES_C);

-- Synchronous Reset
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -159,7 +160,7 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G and axisRst = '1') then
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(axisClk) then
r <= rin after TPD_G;
Expand Down
7 changes: 4 additions & 3 deletions base/crc/rtl/Crc32.vhd
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Expand Up @@ -34,13 +34,14 @@ use surf.CrcPkg.all;
entity Crc32 is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
BYTE_WIDTH_G : positive := 4;
INPUT_REGISTER_G : boolean := true;
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF";
CRC_POLY_G : slv(31 downto 0) := x"04C11DB7");
port (
crcPwrOnRst : in sl := '0';
crcPwrOnRst : in sl := not RST_POLARITY_G;
crcOut : out slv(31 downto 0); -- CRC output
crcRem : out slv(31 downto 0); -- CRC interim remainder
crcClk : in sl; -- system clock
Expand Down Expand Up @@ -146,10 +147,10 @@ begin

seq : process (crcClk, crcPwrOnRst) is
begin
if (RST_ASYNC_G and crcPwrOnRst = '1') then
if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif (rising_edge(crcClk)) then
if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
else
r <= rin after TPD_G;
Expand Down
7 changes: 4 additions & 3 deletions base/crc/rtl/Crc32Parallel.vhd
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Expand Up @@ -40,12 +40,13 @@ use surf.CrcPkg.all;
entity Crc32Parallel is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
BYTE_WIDTH_G : positive := 4;
INPUT_REGISTER_G : boolean := true;
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF");
port (
crcPwrOnRst : in sl := '0';
crcPwrOnRst : in sl := not RST_POLARITY_G;
crcOut : out slv(31 downto 0); -- CRC output
crcRem : out slv(31 downto 0); -- CRC interim remainder
crcClk : in sl; -- system clock
Expand Down Expand Up @@ -188,10 +189,10 @@ begin

seq : process (crcClk, crcPwrOnRst) is
begin
if (RST_ASYNC_G and crcPwrOnRst = '1') then
if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif (rising_edge(crcClk)) then
if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
else
r <= rin after TPD_G;
Expand Down
5 changes: 3 additions & 2 deletions base/general/rtl/Scrambler.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ use surf.StdRtlPkg.all;
entity Scrambler is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
DIRECTION_G : string := "SCRAMBLER"; -- or DESCRAMBLER
DATA_WIDTH_G : integer := 64;
Expand Down Expand Up @@ -129,7 +130,7 @@ begin
inputReady <= v.inputReady;

-- Reset
if (RST_ASYNC_G = false and rst = '1') then
if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
v := REG_INIT_C;
end if;

Expand All @@ -150,7 +151,7 @@ begin

seq : process (clk, rst) is
begin
if (RST_ASYNC_G and rst = '1') then
if (RST_ASYNC_G and rst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif rising_edge(clk) then
r <= rin after TPD_G;
Expand Down
7 changes: 5 additions & 2 deletions base/sync/rtl/RstSync.vhd
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Expand Up @@ -4,6 +4,9 @@
-- Description: Synchronizes the trailing edge of an asynchronous reset to a
-- given clock.
-------------------------------------------------------------------------------
-- Note: Using "std_logic" instead of "sl" for generics due to issues with
-- SystemVerilog handling VHDL subtype on generics properly
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
Expand All @@ -22,8 +25,8 @@ use surf.StdRtlPkg.all;
entity RstSync is
generic (
TPD_G : time := 1 ns; -- Simulation FF output delay
IN_POLARITY_G : sl := '1'; -- 0 for active low rst, 1 for high
OUT_POLARITY_G : sl := '1';
IN_POLARITY_G : std_logic := '1'; -- 0 for active low rst, 1 for high
OUT_POLARITY_G : std_logic := '1';
BYPASS_SYNC_G : boolean := false; -- Bypass Synchronizer module for synchronous data configuration
RELEASE_DELAY_G : integer range 3 to positive'high := 3; -- Delay between deassertion of async and sync resets
OUT_REG_RST_G : boolean := true); -- Apply async reset to final reg stage
Expand Down
40 changes: 21 additions & 19 deletions base/sync/rtl/SynchronizerFifo.vhd
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Expand Up @@ -22,18 +22,19 @@ use surf.StdRtlPkg.all;

entity SynchronizerFifo is
generic (
TPD_G : time := 1 ns;
RST_ASYNC_G : boolean := false;
COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration
MEMORY_TYPE_G : string := "distributed";
SYNC_STAGES_G : integer range 3 to (2**24) := 3;
PIPE_STAGES_G : natural range 0 to 16 := 0;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
ADDR_WIDTH_G : integer range 2 to 48 := 4;
INIT_G : slv := "0");
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration
MEMORY_TYPE_G : string := "distributed";
SYNC_STAGES_G : integer range 3 to (2**24) := 3;
PIPE_STAGES_G : natural range 0 to 16 := 0;
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
ADDR_WIDTH_G : integer range 2 to 48 := 4;
INIT_G : slv := "0");
port (
-- Asynchronous Reset
rst : in sl := '0';
rst : in sl := not RST_POLARITY_G;
-- Write Ports (wr_clk domain)
wr_clk : in sl;
wr_en : in sl := '1';
Expand All @@ -58,15 +59,16 @@ begin

FifoAsync_1 : entity surf.FifoAsync
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
FWFT_EN_G => true,
SYNC_STAGES_G => SYNC_STAGES_G,
PIPE_STAGES_G => PIPE_STAGES_G,
DATA_WIDTH_G => DATA_WIDTH_G,
ADDR_WIDTH_G => ADDR_WIDTH_G,
INIT_G => INIT_C)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
FWFT_EN_G => true,
SYNC_STAGES_G => SYNC_STAGES_G,
PIPE_STAGES_G => PIPE_STAGES_G,
DATA_WIDTH_G => DATA_WIDTH_G,
ADDR_WIDTH_G => ADDR_WIDTH_G,
INIT_G => INIT_C)
port map (
rst => rst,
wr_clk => wr_clk,
Expand Down
44 changes: 25 additions & 19 deletions protocols/packetizer/rtl/AxiStreamDepacketizer2.vhd
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Expand Up @@ -30,6 +30,7 @@ use surf.AxiStreamPacketizer2Pkg.all;
entity AxiStreamDepacketizer2 is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
RST_ASYNC_G : boolean := false;
MEMORY_TYPE_G : string := "distributed";
REG_EN_G : boolean := false;
Expand Down Expand Up @@ -159,9 +160,10 @@ begin
-----------------
U_Input : entity surf.AxiStreamPipeline
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => INPUT_PIPE_STAGES_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => INPUT_PIPE_STAGES_G)
port map (
axisClk => axisClk,
axisRst => axisRst,
Expand All @@ -186,15 +188,16 @@ begin
GEN_SEQ : if (SEQ_CNT_SIZE_G > 0) generate
U_DualPortRam_1 : entity surf.DualPortRam
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
REG_EN_G => REG_EN_G,
DOA_REG_G => REG_EN_G,
DOB_REG_G => REG_EN_G,
BYTE_WR_EN_G => false,
DATA_WIDTH_G => RAM_DATA_WIDTH_C,
ADDR_WIDTH_G => ADDR_WIDTH_C)
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
RST_POLARITY_G => RST_POLARITY_G,
MEMORY_TYPE_G => MEMORY_TYPE_G,
REG_EN_G => REG_EN_G,
DOA_REG_G => REG_EN_G,
DOB_REG_G => REG_EN_G,
BYTE_WR_EN_G => false,
DATA_WIDTH_G => RAM_DATA_WIDTH_C,
ADDR_WIDTH_G => ADDR_WIDTH_C)
port map (
clka => axisClk,
rsta => axisRst,
Expand All @@ -207,10 +210,10 @@ begin
NO_SEQ : if (SEQ_CNT_SIZE_G = 0) generate
process (axisClk, axisRst) is
begin
if (RST_ASYNC_G and axisRst = '1') then
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
ramDout <= (others => '0') after TPD_G;
elsif (rising_edge(axisClk)) then
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
ramDout <= (others => '0') after TPD_G;
else
ramDout <= ramDin after TPD_G;
Expand All @@ -228,6 +231,7 @@ begin
U_Crc32 : entity surf.Crc32Parallel
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
INPUT_REGISTER_G => false,
BYTE_WIDTH_G => 8,
Expand All @@ -248,6 +252,7 @@ begin
U_Crc32 : entity surf.Crc32
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
INPUT_REGISTER_G => false,
BYTE_WIDTH_G => 8,
Expand Down Expand Up @@ -649,10 +654,10 @@ begin

seq : process (axisClk, axisRst) is
begin
if (RST_ASYNC_G and axisRst = '1') then
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
elsif (rising_edge(axisClk)) then
if (RST_ASYNC_G = false and axisRst = '1') then
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
r <= REG_INIT_C after TPD_G;
else
r <= rin after TPD_G;
Expand All @@ -665,9 +670,10 @@ begin
------------------
U_Output : entity surf.AxiStreamPipeline
generic map (
TPD_G => TPD_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G)
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => RST_ASYNC_G,
PIPE_STAGES_G => OUTPUT_PIPE_STAGES_G)
port map (
axisClk => axisClk,
axisRst => axisRst,
Expand Down
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