Minor Fixes (#499)

* Fixes disassembler of hor64 to be immediate instead of register. * Fixes sign extension in emit_product_quotient_remainder().
solana-labs · Aug 10, 2023 · 91f8af8 · 91f8af8
1 parent 0c64b48
commit 91f8af8
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Showing 2 changed files with 8 additions and 6 deletions.
diff --git a/src/disassembler.rs b/src/disassembler.rs
@@ -200,7 +200,7 @@ pub fn disassemble_instruction<C: ContextObject>(
         ebpf::MOV64_REG  => { name = "mov64";  desc = alu_reg_str(name, insn); },
         ebpf::ARSH64_IMM => { name = "arsh64"; desc = alu_imm_str(name, insn); },
         ebpf::ARSH64_REG => { name = "arsh64"; desc = alu_reg_str(name, insn); },
-        ebpf::HOR64_IMM  => { name = "hor64"; desc = alu_reg_str(name, insn); },
+        ebpf::HOR64_IMM  => { name = "hor64"; desc = alu_imm_str(name, insn); },
 
         // BPF_JMP class
         ebpf::JA         => {

diff --git a/src/jit.rs b/src/jit.rs
@@ -1169,7 +1169,7 @@ impl<'a, V: Verifier, C: ContextObject> JitCompiler<'a, V, C> {
         // dst-in  RAX  RAX   RAX   RAX  RAX  RAX  RAX
         // dst-out RAX  RDX   RDX   RAX  RAX  RDX  RDX
 
-        let signed = (opc & ebpf::BPF_ALU_OP_MASK) == ebpf::BPF_SDIV;
+        let signed = (opc & ebpf::BPF_ALU_OP_MASK) == ebpf::BPF_MUL || (opc & ebpf::BPF_ALU_OP_MASK) == ebpf::BPF_SDIV;
         let division = (opc & ebpf::BPF_ALU_OP_MASK) != ebpf::BPF_MUL;
         let alt_dst = (opc & ebpf::BPF_ALU_OP_MASK) == ebpf::BPF_MOD;
         let size = if (opc & ebpf::BPF_CLS_MASK) == ebpf::BPF_ALU64 { OperandSize::S64 } else { OperandSize::S32 };
@@ -1221,10 +1221,12 @@ impl<'a, V: Verifier, C: ContextObject> JitCompiler<'a, V, C> {
         if dst != RDX {
             self.emit_ins(X86Instruction::push(RDX, None));
         }
-        if signed {
-            self.emit_ins(X86Instruction::sign_extend_rax_rdx(size));
-        } else if division {
-            self.emit_ins(X86Instruction::alu(size, 0x31, RDX, RDX, 0, None)); // RDX = 0
+        if division {
+            if signed {
+                self.emit_ins(X86Instruction::sign_extend_rax_rdx(size));
+            } else {
+                self.emit_ins(X86Instruction::alu(size, 0x31, RDX, RDX, 0, None)); // RDX = 0
+            }
         }
 
         self.emit_ins(X86Instruction::alu(size, 0xf7, 0x4 | (division as u8) << 1 | signed as u8, R11, 0, None));