Fix load when enable_address_translation is false. (#474)

solana-labs · Jun 21, 2023 · f91d598 · f91d598
1 parent 8569f7e
commit f91d598
Showing 1 changed file with 14 additions and 13 deletions.
diff --git a/src/jit.rs b/src/jit.rs
@@ -978,6 +978,8 @@ impl<'a, V: Verifier, C: ContextObject> JitCompiler<'a, V, C> {
 
     #[inline]
     fn emit_address_translation(&mut self, dst: Option<u8>, vm_addr: Value, len: u64, value: Option<Value>) {
+        debug_assert_ne!(dst.is_some(), value.is_some());
+
         match vm_addr {
             Value::RegisterPlusConstant64(reg, constant, user_provided) => {
                 if user_provided && self.should_sanitize_constant(constant) {
@@ -1019,27 +1021,26 @@ impl<'a, V: Verifier, C: ContextObject> JitCompiler<'a, V, C> {
             let anchor = ANCHOR_TRANSLATE_MEMORY_ADDRESS + len.trailing_zeros() as usize + 4 * (access_type as usize);
             self.emit_ins(X86Instruction::push_immediate(OperandSize::S64, self.pc as i32));
             self.emit_ins(X86Instruction::call_immediate(self.relative_to_anchor(anchor, 5)));
-        } else if value.is_some() {
+            if let Some(dst) = dst {
+                self.emit_ins(X86Instruction::mov(OperandSize::S64, R11, dst));
+            }
+        } else if let Some(dst) = dst {
             match len {
-                1 => self.emit_ins(X86Instruction::store(OperandSize::S8, R10, R11, X86IndirectAccess::Offset(0))),
-                2 => self.emit_ins(X86Instruction::store(OperandSize::S16, R10, R11, X86IndirectAccess::Offset(0))),
-                4 => self.emit_ins(X86Instruction::store(OperandSize::S32, R10, R11, X86IndirectAccess::Offset(0))),
-                8 => self.emit_ins(X86Instruction::store(OperandSize::S64, R10, R11, X86IndirectAccess::Offset(0))),
+                1 => self.emit_ins(X86Instruction::load(OperandSize::S8, R11, dst, X86IndirectAccess::Offset(0))),
+                2 => self.emit_ins(X86Instruction::load(OperandSize::S16, R11, dst, X86IndirectAccess::Offset(0))),
+                4 => self.emit_ins(X86Instruction::load(OperandSize::S32, R11, dst, X86IndirectAccess::Offset(0))),
+                8 => self.emit_ins(X86Instruction::load(OperandSize::S64, R11, dst, X86IndirectAccess::Offset(0))),
                 _ => unreachable!(),
             }
         } else {
             match len {
-                1 => self.emit_ins(X86Instruction::load(OperandSize::S8, R11, R10, X86IndirectAccess::Offset(0))),
-                2 => self.emit_ins(X86Instruction::load(OperandSize::S16, R11, R10, X86IndirectAccess::Offset(0))),
-                4 => self.emit_ins(X86Instruction::load(OperandSize::S32, R11, R10, X86IndirectAccess::Offset(0))),
-                8 => self.emit_ins(X86Instruction::load(OperandSize::S64, R11, R10, X86IndirectAccess::Offset(0))),
+                1 => self.emit_ins(X86Instruction::store(OperandSize::S8, R10, R11, X86IndirectAccess::Offset(0))),
+                2 => self.emit_ins(X86Instruction::store(OperandSize::S16, R10, R11, X86IndirectAccess::Offset(0))),
+                4 => self.emit_ins(X86Instruction::store(OperandSize::S32, R10, R11, X86IndirectAccess::Offset(0))),
+                8 => self.emit_ins(X86Instruction::store(OperandSize::S64, R10, R11, X86IndirectAccess::Offset(0))),
                 _ => unreachable!(),
             }
         }
-
-        if let Some(dst) = dst {
-            self.emit_ins(X86Instruction::mov(OperandSize::S64, R11, dst));
-        }
     }
 
     #[inline]