Updated documentation on ETH FPGA Card.

sqdlab · Jul 22, 2024 · f6d3869 · f6d3869
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diff --git a/docs/User/InstrumentSpecific/ETH_FPGA_Card.md b/docs/User/InstrumentSpecific/ETH_FPGA_Card.md
@@ -29,6 +29,7 @@ If during operation, the card throws an error, reset the FPGA using any/all of t
 - fpga.reset()
 
 
+
 ## Setting up the client
 
 YAML entry:
@@ -40,7 +41,22 @@ YAML entry:
       uri: 'Z:/DataAnalysis/Notebooks/qcodes/FPGA_Rack1_URI.txt'
 ```
 
-Make sure to set the correct path for the URI.
+Make sure to set the correct path for the URI. The typical connection setup looks like:
+
+![My Diagram3](ETH_FPGA_setup.drawio.svg)
+
+The frequency multiplier box is required to provide the 100MSPS sample clock.
+
+## Maintaining the connectors
+
+There is a jumper header that connects to the four BNC ports in the FPGA card on `J10`. Check the integrity of this connector regularly during maintenance:
+
+![My Diagram3](ETH_FPGA_connector.drawio.svg)
+
+The ground pins are tied together internally and can be connected to the BNC shields of all 4 BNC connectors.
+
+
+## Test setup
 
 The AWG can be used to check the working of and to reprogram the fpga, the wiring for which is shown below
 

diff --git a/docs/User/InstrumentSpecific/ETH_FPGA_connector.drawio.svg b/docs/User/InstrumentSpecific/ETH_FPGA_connector.drawio.svg