Added support for G031/G041 chips (#825)

stlink-org · Feb 20, 2020 · 03ef7bd · 03ef7bd
2 parents dfd8512 + 156871d
commit 03ef7bd
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Showing 3 changed files with 24 additions and 3 deletions.
diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
@@ -70,10 +70,11 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_L011             = 0x457,
 	STLINK_CHIPID_STM32_F410             = 0x458,
 	STLINK_CHIPID_STM32_F413             = 0x463,
-	STLINK_CHIPID_STM32_L4RX             = 0x470, // taken from the STM32L4R9I-DISCO board
-	STLINK_CHIPID_STM32_G0X1             = 0x460,
+	STLINK_CHIPID_STM32_G0_CAT1          = 0x466, // G031/041
+	STLINK_CHIPID_STM32_G0_CAT2          = 0x460, // G071/081
 	STLINK_CHIPID_STM32_G4_CAT2          = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code".
 	STLINK_CHIPID_STM32_G4_CAT3          = 0x469,
+	STLINK_CHIPID_STM32_L4RX             = 0x470, // taken from the STM32L4R9I-DISCO board
 	STLINK_CHIPID_STM32_WB55             = 0x495
 };
 

diff --git a/src/chipid.c b/src/chipid.c
@@ -521,9 +521,20 @@ static const struct stlink_chipid_params devices[] = {
             .bootrom_base = 0x1ff00000,
             .bootrom_size = 0x2000
         },
+        {
+            // STM32G031/041 (from RM0444)
+            .chip_id = STLINK_CHIPID_STM32_G0_CAT1,
+            .description = "G031/G041 device",
+            .flash_type = STLINK_FLASH_TYPE_G0,
+            .flash_size_reg = 0x1FFF75E0,    // Section 38.2
+            .flash_pagesize = 0x800,         // 2K (sec 3.2)
+            .sram_size = 0x2000,             // 8K (sec 2.3)
+            .bootrom_base = 0x1fff0000,
+            .bootrom_size = 0x7800           // 30K (table 3)
+        },
         {
             // STM32G071/081 (from RM0444)
-            .chip_id = STLINK_CHIPID_STM32_G0X1,
+            .chip_id = STLINK_CHIPID_STM32_G0_CAT2,
             .description = "G071/G081 device",
             .flash_type = STLINK_FLASH_TYPE_G0,
             .flash_size_reg = 0x1FFF75E0,    // Section 38.2

diff --git a/src/common.c b/src/common.c
@@ -2577,6 +2577,15 @@ static int stlink_write_option_bytes_g0x1(stlink_t *sl, uint8_t* base, uint32_t
         return -1;
     }
 
+    // Make sure we've loaded the context with the chip details
+    stlink_core_id(sl);
+
+    /* Check if chip is supported and for correct address */
+    if((sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1) || (addr != STM32_G0_OPTION_BYTES_BASE)) {
+        ELOG("Option bytes writing is currently only supported for the STM32G0\n");
+        return -1;
+    }
+
     /* Unlock flash if necessary (ref manuel page 52) */
     stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val);
     if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) {