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- [doc] Update on OS version support - Minor fixes for G0-series from #1293 - [doc] Added core-IDs for WB/WL-series - [doc] Correction for G0/L0-series core-IDs - Set option_size to 128 B for G0-series (#1194)
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,14 +1,14 @@ | ||
# Chip-ID file for STM32G05x / STM32G06x device | ||
# | ||
dev_type STM32G05x_G06x | ||
ref_manual_id 0444 | ||
ref_manual_id 0444 // also RM454 | ||
chip_id 0x456 // STM32_CHIPID_G0_CAT4 | ||
flash_type G0 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0x9000 // 36 KB | ||
sram_size 0x4800 // 18 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE | ||
option_size 0x4 // 4 B | ||
option_size 0x80 // 128 B | ||
flags none |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,14 +1,14 @@ | ||
# Chip-ID file for STM32G0Bx / STM32G0Cx device | ||
# | ||
dev_type STM32G0Bx_G0Cx | ||
ref_manual_id 0444 | ||
ref_manual_id 0444 // also RM454 | ||
chip_id 0x467 // STM32_CHIPID_G0_CAT3 | ||
flash_type G0 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0x9000 // 36 KB | ||
sram_size 0x24000 // 144 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE | ||
option_size 0x4 // 4 B | ||
option_size 0x80 // 128 B | ||
flags dualbank |
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