stm32g4: read flash optr to get flash bank mode on cat3 devices.

g4 cat3 devices can be configured in two mode via option bytes:
  - dual bank, 2x256kib, 2KiB pages.
  - single bank, 1x512KiB, 4KiB pages.
in anycase, these have two banks, and need to be handled with more care.

-> read optr after loading flash params to patch page size.
-> in single bank mode, mass erase _must_ be triggered by applying
MER1 and MER2 bits. erasing half of the flash will lead to a pgserr.

src/chipid.c

@@ -562,6 +562,7 @@ static const struct stlink_chipid_params devices[] = {
             .chip_id = STLINK_CHIPID_STM32_G4_CAT3,
             .description = "G4 Category-3",
             .flash_type = STLINK_FLASH_TYPE_G4,
+            .has_dual_bank = true,
             .flash_size_reg = 0x1FFF75E0,    // Section 47.2
             .flash_pagesize = 0x800,         // 2K (sec 3.3.1)
             // SRAM1 is 80k at 0x20000000

src/common.c

@@ -128,9 +128,13 @@
 #define STM32Gx_FLASH_CR_OBL_LAUNCH (27)      /* Forces the option byte loading */
 #define STM32Gx_FLASH_CR_OPTLOCK    (30)      /* Options Lock */
 #define STM32Gx_FLASH_CR_LOCK       (31)      /* FLASH_CR Lock */
+
 // G0/G4 FLASH status register
 #define STM32Gx_FLASH_SR_BSY        (16)      /* FLASH_SR Busy */
 
+// G4 FLASH option register
+#define STM32G4_FLASH_OPTR_DBANK    (22)      /* FLASH_OPTR Dual Bank Mode */
+
 // WB (RM0434)
 #define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000)
 #define STM32WB_FLASH_ACR       (STM32WB_FLASH_REGS_ADDR + 0x00)
@@ -899,6 +903,14 @@ int stlink_load_device_params(stlink_t *sl) {
         sl->sram_size = 0x1000;
     }
 
+    if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) {
+        uint32_t flash_optr;
+        stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr);
+        if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) {
+            sl->flash_pgsz <<= 1;
+        }
+    }
+
 #if 0
     // Old code -- REW
     ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);