Minor changes & fixes

- Simplified listing of supported devices - Corrected #define STM32L5_PWR_CR1_VOS - Check the return code of stlink_read_debug32 - Fix for flash register reading on L5x2 devices
stlink-org · Apr 4, 2023 · 8af1dcb · 8af1dcb
1 parent e93fa57
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diff --git a/doc/devices_boards.md b/doc/devices_boards.md
diff --git a/doc/supported devices.md b/doc/supported devices.md
@@ -0,0 +1,59 @@
+# MCUs supported by the STlink toolset
+
+A list of devices supported by the stlink toolset can be found in */inc/stm32.h*.
+More commonly these are:
+
+| Product-Family | ARM Cortex Core | Product Line                                               |
+| -------------- | --------------- | ---------------------------------------------------------- |
+| STM32F0        | M0              |                                                            |
+| STM32G0        | M0+             |                                                            |
+| STM32L0        | M0+             |                                                            |
+| STM32F10**0**  | M3              | Value line                                                 |
+| STM32F10**1**  | M3              | Access line                                                |
+| STM32F10**2**  | M3              | USB Access line                                            |
+| STM32F10**3**  | M3              | Performance line                                           |
+| STM32F10**5**  | M3              | Connectivity line                                          |
+| STM32F10**7**  | M3              | Connectivity line                                          |
+| STM32L1        | M3              |                                                            |
+| STM32F2        | M3              |                                                            |
+| STM32F3**01**  | M4F             | Access line                                                |
+| STM32F3**02**  | M4F             | USB & CAN line                                             |
+| STM32F3**03**  | M4F             | Performance line                                           |
+| STM32F3**34**  | M4F             | Digital Power line                                         |
+| STM32F3**73**  | M4F             | Precision Measurement line (64k/16k / 128k/24k / 265k/32k) |
+| STM32F3**18**  | M4F             | General Purpose line (64k/16k)                             |
+| STM32F3**28**  | M4F             | General Purpose line (64k/16k)                             |
+| STM32F3**58**  | M4F             | General Purpose line (265k/48k)                            |
+| STM32F3**78**  | M4F             | Precision Measurement line (265k/32k)                      |
+| STM32F3**98**  | M4F             | General Purpose line (512k/80k)                            |
+| STM32F4        | M4F             |                                                            |
+| STM32G4        | M4F             |                                                            |
+| STM32L4        | M4F             |                                                            |
+| STM32F7        | M4F             |                                                            |
+| STM32H7        | M4F             |                                                            |
+| STM32WB        | M4F             |                                                            |
+| STM32WL        | M4              |                                                            |
+
+
+# Chinese Clone-Chips [may work, but without support!]
+
+## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) (mostly on Bluepill-Boards)
+
+**(!) Attention:** Some MCUs may come with with _**Fake-STM32-Marking !**_
+
+**(!) Attention:** The Core-ID of these MCUs is in conflict with the one of the original STM32F1-devices.
+
+| Product-Code  | Chip-ID | Comment                                                                   |
+| ------------- | ------- | ------------------------------------------------------------------------- |
+| CKS32F103C8T6 | 0x410   | STM32F103C8T6 clone from China Key Systems (CKS)                          |
+| CH32F103C8T6  | 0x410   | STM32F103C8T6 clone from Nanjing Qinheng Microelectronics Co., Ltd. (WCH) |
+
+## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477)
+
+**(!) Attention:** The Chip-IDs of these MCUs are in conflict with such of original STM32F1-devices.
+
+| Product-Code | Chip-ID | Comment                              |
+| ------------ | ------- | ------------------------------------ |
+| GD32F303VET6 | 0x414   | STM32F303 clone from GigaDevice (GD) |
+| GD32F303CGT6 | 0x430   | STM32F303 clone from GigaDevice (GD) |
+| GD32F303VGT6 | 0x430   | STM32F303 clone from GigaDevice (GD) |
diff --git a/inc/stm32.h b/inc/stm32.h
@@ -215,6 +215,6 @@ enum stm32_chipids {
 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
 
 #define STM32L5_PWR_CR1 0x40007000                      // RM0438, p. 93,324
-#define STM32L5_PWR_CR1_VOS 8
+#define STM32L5_PWR_CR1_VOS 9
 
 #endif // STM32_H
diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c
@@ -292,6 +292,15 @@ int stlink_load_device_params(stlink_t *sl) {
     }
   }
 
+  if (sl->chip_id == STM32_CHIPID_L5x2xx) {
+    uint32_t flash_optr;
+    stlink_read_debug32(sl, STM32L5_FLASH_OPTR, &flash_optr);
+
+    if (sl->flash_size == 512*1024 && (flash_optr & (1 << 22)) != 0) {
+      sl->flash_pgsz = 0x800;
+    }
+  }
+
   // H7 devices with small flash has one bank
   if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK &&
       sl->flash_type == STM32_FLASH_TYPE_H7) {

diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c
@@ -441,8 +441,7 @@ static void unlock_flash(stlink_t *sl) {
     // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183)
     uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS);
     uint32_t val;
-    stlink_read_debug32(sl, STM32L5_PWR_CR1, &val);
-    if ((val & mask) > (1 << STM32L5_PWR_CR1_VOS)) {
+    if (!stlink_read_debug32(sl, STM32L5_PWR_CR1, &val) && (val & mask) > (1 << STM32L5_PWR_CR1_VOS)) {
       val &= ~mask;
       stlink_write_debug32(sl, STM32L5_PWR_CR1, val);
     }