Merge branch 'WRansohoff-stlink_g0_soic8' into stm32g0_support

Merged PR #825.
stlink-org · Mar 16, 2020 · b58c14a · b58c14a
2 parents 85f212f + 85d33b2
commit b58c14a
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Showing 4 changed files with 3 additions and 3 deletions.
diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
@@ -75,6 +75,8 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_G4_CAT2          = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code".
 	STLINK_CHIPID_STM32_G4_CAT3          = 0x469,
 	STLINK_CHIPID_STM32_L4RX             = 0x470, // taken from the STM32L4R9I-DISCO board
+	STLINK_CHIPID_STM32_G0_CAT1          = 0x466, // G031/041
+	STLINK_CHIPID_STM32_G0_CAT2          = 0x460, // G071/081
 	STLINK_CHIPID_STM32_WB55             = 0x495
 };
 

diff --git a/include/stm32.h b/include/stm32.h
@@ -9,7 +9,6 @@
 
 // cortex core ids
 #define STM32VL_CORE_ID 0x1ba01477
-#define CS32VL_CORE_ID 0x2ba01477
 #define STM32F7_CORE_ID 0x5ba02477
 
 // Constant STM32 memory map figures

diff --git a/src/common.c b/src/common.c
@@ -2637,7 +2637,7 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l
 
     /* Check if chip is supported and for correct address */
     if(sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 &&
-        sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) {
+       sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) {
         ELOG("Option bytes writing is currently only supported for the STM32G0\n");
         return -1;
     }

diff --git a/src/flash_loader.c b/src/flash_loader.c
@@ -267,7 +267,6 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
         loader_code = loader_code_stm32l;
         loader_size = sizeof(loader_code_stm32l);
     } else if (sl->core_id == STM32VL_CORE_ID ||
-               sl->core_id == CS32VL_CORE_ID ||
                sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM ||
                sl->chip_id == STLINK_CHIPID_STM32_F3 ||
                sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL ||