Added support for STM32L4Q5 (Closes #1224)

config/chips/L41x_L42x.chip

@@ -3,7 +3,7 @@
 dev_type STM32L41x_L42x
 ref_manual_id 0394
 chip_id 0x464                // STM32_CHIPID_L41x_L42x
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x800         // 2 KB
 sram_size 0xa000             // 40 KB

config/chips/L43x_L44x.chip

@@ -3,7 +3,7 @@
 dev_type STM32L41x_L42x
 ref_manual_id 0392
 chip_id 0x435                // STM32_CHIPID_L43x_L44x
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x800         // 2 KB
 sram_size 0xc000             // 48 KB

config/chips/L45x_L46x.chip

@@ -3,7 +3,7 @@
 dev_type STM32L45x_L46x
 ref_manual_id 0394
 chip_id 0x462                // STM32_CHIPID_L45x_L46x
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x800         // 2 KB
 sram_size 0x20000            // 128 KB

config/chips/L47x_L48x.chip

@@ -3,7 +3,7 @@
 dev_type STM32L47x_L48x
 ref_manual_id 0351
 chip_id 0x415                // STM32_CHIPID_L4
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x800         // 2 KB
 sram_size 0x18000            // 96 KB

config/chips/L496x_L4A6x.chip

@@ -3,7 +3,7 @@
 dev_type STM32L496x_L4A6x
 ref_manual_id 0351
 chip_id 0x461                // STM32_CHIPID_L496x_L4A6x
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x800         // 2 KB
 sram_size 0x50000            // 320 KB

config/chips/L4Px.chip → config/chips/L4Px_L4Qx.chip

@@ -1,14 +1,14 @@
-# Chip-ID file for STM32L4Px device
+# Chip-ID file for STM32L4Px / STM32L4Qx device
 #
-dev_type STM32L4Px
+dev_type STM32L4Px_L4Qx
 ref_manual_id 0432
 chip_id 0x471                // STM32_CHIPID_L4PX
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x1000        // 4 KB
 sram_size 0xa0000            // 640 KB
 bootrom_base 0x1fff0000
 bootrom_size 0x7000          // 28 KB
-option_base 0x0
-option_size 0x0
+option_base 0x1ff00000
+option_size 0x4              // 4 B
 flags swo

config/chips/L4Rx.chip

@@ -3,7 +3,7 @@
 dev_type STM32L4Rx
 ref_manual_id 0432
 chip_id 0x470                // STM32_CHIPID_L4RX
-flash_type L4_L4P
+flash_type L4
 flash_size_reg 0x1fff75e0
 flash_pagesize 0x1000        // 4 KB
 sram_size 0xa0000            // 640 KB

inc/stm32.h

@@ -51,7 +51,7 @@ enum stm32_flash_type {
     STM32_FLASH_TYPE_G4        =  6,
     STM32_FLASH_TYPE_H7        =  7,
     STM32_FLASH_TYPE_L0_L1     =  8,
-    STM32_FLASH_TYPE_L4_L4P    =  9,
+    STM32_FLASH_TYPE_L4        =  9,
     STM32_FLASH_TYPE_L5_U5     = 10,
     STM32_FLASH_TYPE_WB_WL     = 11,
 };

src/stlink-lib/chipid.c

@@ -100,7 +100,7 @@ void process_chipfile(char *fname) {
             } else if (strcmp(value, "L0_L1") == 0) {
                 ts->flash_type = STM32_FLASH_TYPE_L0_L1;
             } else if (strcmp(value, "L4_L4P") == 0) {
-                ts->flash_type = STM32_FLASH_TYPE_L4_L4P;
+                ts->flash_type = STM32_FLASH_TYPE_L4;
             } else if (strcmp(value, "L5_U5") == 0) {
                 ts->flash_type = STM32_FLASH_TYPE_L5_U5;
             } else if (strcmp(value, "WB_WL") == 0) {

src/stlink-lib/common.c

@@ -984,7 +984,7 @@ static void stop_wdg_in_debug(stlink_t *sl) {
     break;
   case STM32_FLASH_TYPE_F2_F4:
   case STM32_FLASH_TYPE_F7:
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1;
     set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) |
           (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP);

src/stlink-lib/common_flash.c

@@ -38,7 +38,7 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) {
     reg = FLASH_F4_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     reg = FLASH_F7_CR;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     reg = STM32L4_FLASH_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
@@ -79,7 +79,7 @@ void lock_flash(stlink_t *sl) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) {
     cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
     cr_lock_shift = STM32L0_FLASH_PELOCK;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     cr_reg = STM32L4_FLASH_CR;
     cr_lock_shift = STM32L4_FLASH_CR_LOCK;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
@@ -124,7 +124,7 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) {
     sr_reg = FLASH_F4_SR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     sr_reg = FLASH_F7_SR;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     sr_reg = STM32L4_FLASH_SR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
@@ -163,7 +163,7 @@ void clear_flash_error(stlink_t *sl) {
       write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK);
     }
     break;
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK);
     break;
   case STM32_FLASH_TYPE_H7:
@@ -192,7 +192,7 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) {
     sr_reg = FLASH_F4_SR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     sr_reg = FLASH_F7_SR;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     sr_reg = STM32L4_FLASH_SR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
@@ -222,7 +222,7 @@ unsigned int is_flash_busy(stlink_t *sl) {
     sr_busy_shift = FLASH_F4_SR_BSY;
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     sr_busy_shift = FLASH_F7_SR_BSY;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     sr_busy_shift = STM32L4_FLASH_SR_BSY;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
@@ -297,7 +297,7 @@ int check_flash_error(stlink_t *sl) {
     WRPERR = (1 << STM32L0_FLASH_SR_WRPERR);
     PGAERR = (1 << STM32L0_FLASH_SR_PGAERR);
     break;
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK;
     WRPERR = (1 << STM32L4_FLASH_SR_WRPERR);
     PROGERR = (1 << STM32L4_FLASH_SR_PROGERR);
@@ -360,7 +360,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) {
     cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
     cr_lock_shift = STM32L0_FLASH_PELOCK;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     cr_reg = STM32L4_FLASH_CR;
     cr_lock_shift = STM32L4_FLASH_CR_LOCK;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
@@ -404,7 +404,7 @@ static void unlock_flash(stlink_t *sl) {
     key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF;
     flash_key1 = FLASH_L0_PEKEY1;
     flash_key2 = FLASH_L0_PEKEY2;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     key_reg = STM32L4_FLASH_KEYR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
@@ -468,7 +468,7 @@ int lock_flash_option(stlink_t *sl) {
     optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
     optlock_shift = STM32L0_FLASH_OPTLOCK;
     break;
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     optcr_reg = STM32L4_FLASH_CR;
     optlock_shift = STM32L4_FLASH_CR_OPTLOCK;
     break;
@@ -541,7 +541,7 @@ static bool is_flash_option_locked(stlink_t *sl) {
     optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF;
     optlock_shift = STM32L0_FLASH_OPTLOCK;
     break;
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     optcr_reg = STM32L4_FLASH_CR;
     optlock_shift = STM32L4_FLASH_CR_OPTLOCK;
     break;
@@ -595,7 +595,7 @@ static int unlock_flash_option(stlink_t *sl) {
     optkey1 = FLASH_L0_OPTKEY1;
     optkey2 = FLASH_L0_OPTKEY2;
     break;
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     optkey_reg = STM32L4_FLASH_OPTKEYR;
     break;
   case STM32_FLASH_TYPE_G0:
@@ -672,7 +672,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) {
     cr_reg = FLASH_F4_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     cr_reg = FLASH_F7_CR;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     cr_reg = STM32L4_FLASH_CR;
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
              sl->flash_type == STM32_FLASH_TYPE_G4) {
@@ -796,7 +796,7 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     cr_reg = FLASH_F7_CR;
     cr_strt = 1 << FLASH_F7_CR_STRT;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     cr_reg = STM32L4_FLASH_CR;
     cr_strt = (1 << STM32L4_FLASH_CR_STRT);
   } else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
@@ -830,7 +830,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) {
     cr_reg = FLASH_F7_CR;
     cr_mer = 1 << FLASH_CR_MER;
     cr_pg = 1 << FLASH_CR_PG;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     cr_reg = STM32L4_FLASH_CR;
     cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
     cr_pg = (1 << STM32L4_FLASH_CR_PG);
@@ -890,7 +890,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
 
   if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 ||
       sl->flash_type == STM32_FLASH_TYPE_F7 ||
-      sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+      sl->flash_type == STM32_FLASH_TYPE_L4) {
     // unlock if locked
     unlock_flash_if(sl);
 

src/stlink-lib/flashloader.c

@@ -80,7 +80,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) {
   } else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
     cr_reg = FLASH_F7_CR;
     x |= 1 << FLASH_CR_PG;
-  } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+  } else if (sl->flash_type == STM32_FLASH_TYPE_L4) {
     cr_reg = STM32L4_FLASH_CR;
     x &= ~STM32L4_FLASH_CR_OPBITS;
     x |= (1 << STM32L4_FLASH_CR_PG);
@@ -123,7 +123,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) {
     rcc_dma_mask = STM32G0_RCC_DMAEN;
     break;
   case STM32_FLASH_TYPE_G4:
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     rcc = STM32G4_RCC_AHB1ENR;
     rcc_dma_mask = STM32G4_RCC_DMAEN;
     break;
@@ -170,7 +170,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) {
 
   if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) ||
       (sl->flash_type == STM32_FLASH_TYPE_F7) ||
-      (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) {
+      (sl->flash_type == STM32_FLASH_TYPE_L4)) {
     ILOG("Starting Flash write for F2/F4/F7/L4\n");
 
     // Flash loader initialisation
@@ -194,7 +194,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) {
       return (-1);
     }
 
-    if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) {
+    if (sl->flash_type == STM32_FLASH_TYPE_L4) {
       // L4 does not have a byte-write mode
       if (voltage < 1710) {
         ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage);
@@ -304,7 +304,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl,
   size_t off;
   if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) ||
       (sl->flash_type == STM32_FLASH_TYPE_F7) ||
-      (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) {
+      (sl->flash_type == STM32_FLASH_TYPE_L4)) {
     size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000;
     for (off = 0; off < len;) {
       size_t size = len - off > buf_size ? buf_size : len - off;
@@ -451,7 +451,7 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) {
       (sl->flash_type == STM32_FLASH_TYPE_F1_XL) ||
       (sl->flash_type == STM32_FLASH_TYPE_F2_F4) ||
       (sl->flash_type == STM32_FLASH_TYPE_F7) ||
-      (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) ||
+      (sl->flash_type == STM32_FLASH_TYPE_L4) ||
       (sl->flash_type == STM32_FLASH_TYPE_WB_WL) ||
       (sl->flash_type == STM32_FLASH_TYPE_G0) ||
       (sl->flash_type == STM32_FLASH_TYPE_G4) ||

src/stlink-lib/option_bytes.c

@@ -795,7 +795,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui
   case STM32_FLASH_TYPE_L0_L1:
     ret = stlink_write_option_bytes_l0(sl, addr, base, len);
     break;
-  case STM32_FLASH_TYPE_L4_L4P:
+  case STM32_FLASH_TYPE_L4:
     ret = stlink_write_option_bytes_l4(sl, addr, base, len);
     break;
   case STM32_FLASH_TYPE_G0: