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[refactoring] Clean-up for chipid files (L1, L4)
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# Chip-ID file for L1xx Cat.1 | ||
# Chip-ID file for STM32L1xx (Cat.1) device (L100C6 / L100R8 / L100RB) | ||
# | ||
chip_id 0x416 | ||
description L1xx Cat.1 | ||
flash_type 5 | ||
flash_pagesize 0x100 | ||
sram_size 0x4000 | ||
dev_type STM32L1xx_Cat_1 | ||
ref_manual_id 0038 | ||
chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD | ||
flash_type 5 // STLINK_FLASH_TYPE_L0 | ||
flash_size_reg 0x1ff8004c | ||
flash_pagesize 0x100 // 128 B | ||
sram_size 0x4000 // 16 KB | ||
bootrom_base 0x1ff00000 | ||
bootrom_size 0x1000 | ||
bootrom_size 0x1000 // 4 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags swo | ||
|
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# Chip-ID file for L1xx Cat.2 | ||
# Chip-ID file for STM32L1xx (Cat.2) device (L100C6-A / L100R8-A / L100RB-A) | ||
# | ||
chip_id 0x429 | ||
description L1xx Cat.2 | ||
flash_type 5 | ||
flash_pagesize 0x100 | ||
sram_size 0x8000 | ||
dev_type STM32L1xx_Cat_2 | ||
ref_manual_id 0038 | ||
chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 | ||
flash_type 5 // STLINK_FLASH_TYPE_L0 | ||
flash_size_reg 0x1ff8004c | ||
flash_pagesize 0x100 // 128 B | ||
sram_size 0x8000 // 32 KB | ||
bootrom_base 0x1ff00000 | ||
bootrom_size 0x1000 | ||
bootrom_size 0x1000 // 4 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags swo | ||
|
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# Chip-ID file for L1xx Cat.3 | ||
# Chip-ID file for STM32L1xx (Cat.3) device (L100RC / L15xxC) | ||
# | ||
chip_id 0x427 | ||
description L1xx Cat.3 | ||
flash_type 5 | ||
flash_pagesize 0x100 | ||
sram_size 0x8000 | ||
dev_type STM32L1xx_Cat_3 | ||
ref_manual_id 0038 | ||
chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS | ||
flash_type 5 // STLINK_FLASH_TYPE_L0 | ||
flash_size_reg 0x1ff800cc | ||
flash_pagesize 0x100 // 128 B | ||
sram_size 0x8000 // 32 KB | ||
bootrom_base 0x1ff00000 | ||
bootrom_size 0x1000 | ||
bootrom_size 0x1000 // 4 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags swo | ||
|
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# Chip-ID file for L1xx Cat.4 | ||
# Chip-ID file for STM32L1xx (Cat.4) device (L15xxD / L162xD) | ||
# | ||
chip_id 0x436 | ||
description L1xx Cat.4 | ||
flash_type 5 | ||
flash_pagesize 0x100 | ||
sram_size 0xc000 | ||
dev_type STM32L1xx_Cat_4 | ||
ref_manual_id 0038 | ||
chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD | ||
flash_type 5 // STLINK_FLASH_TYPE_L0 | ||
flash_size_reg 0x1ff800cc | ||
flash_pagesize 0x100 // 128 B | ||
sram_size 0xc000 // 48 KB | ||
bootrom_base 0x1ff00000 | ||
bootrom_size 0x1000 | ||
option_base 0x1ff80000 | ||
option_size 0x8 | ||
bootrom_size 0x1000 // 4 KB | ||
option_base 0x1ff80000 // STM32_L1_OPTION_BYTES_BASE | ||
option_size 0x8 // 8 B | ||
flags swo | ||
|
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# Chip-ID file for L1xx Cat.5 | ||
# Chip-ID file for STM32L1xx (Cat.5) device (L15xxE / L162xE) | ||
# | ||
chip_id 0x437 | ||
description L1xx Cat.5 | ||
flash_type 5 | ||
flash_pagesize 0x100 | ||
sram_size 0x14000 | ||
dev_type STM32L1xx_Cat_5 | ||
ref_manual_id 0038 | ||
chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE | ||
flash_type 5 // STLINK_FLASH_TYPE_L0 | ||
flash_size_reg 0x1ff800cc | ||
flash_pagesize 0x100 // 128 B | ||
sram_size 0x14000 // 80 KB | ||
bootrom_base 0x1ff00000 | ||
bootrom_size 0x1000 | ||
bootrom_size 0x1000 // 4 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags swo | ||
|
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# Chip-ID file for L41x/L42x | ||
# Chip-ID file for STM32L41x / STM32L42x device | ||
# | ||
chip_id 0x464 | ||
description L41x/L42x | ||
flash_type 6 | ||
flash_pagesize 0x800 | ||
sram_size 0xa000 | ||
dev_type STM32L41x_L42x | ||
ref_manual_id 0394 | ||
chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0xa000 // 40 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags swo | ||
|
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# Chip-ID file for L43x/L44x | ||
# Chip-ID file for STM32L43x / STM32L44x device | ||
# | ||
chip_id 0x435 | ||
description L43x/L44x | ||
flash_type 6 | ||
flash_pagesize 0x800 | ||
sram_size 0xc000 | ||
dev_type STM32L41x_L42x | ||
ref_manual_id 0392 | ||
chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0xc000 // 48 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 | ||
option_base 0x1fff7800 | ||
option_size 0x4 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE | ||
option_size 0x4 // 4 B | ||
flags swo | ||
|
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# Chip-ID file for STM32L45x / STM32L46x device | ||
# | ||
dev_type STM32L45x_L46x | ||
ref_manual_id 0394 | ||
chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0x20000 // 128 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags swo |
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# Chip-ID file for L47x/L48x | ||
# Chip-ID file for STM32L47x / STM32L48x device | ||
# | ||
chip_id 0x415 | ||
description L47x/L48x | ||
flash_type 6 | ||
flash_pagesize 0x800 | ||
sram_size 0x18000 | ||
dev_type STM32L47x_L48x | ||
ref_manual_id 0351 | ||
chip_id 0x415 // STLINK_CHIPID_STM32_L4 | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0x18000 // 96 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 | ||
option_base 0x1fff7800 | ||
option_size 0x4 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE | ||
option_size 0x4 // 4 B | ||
flags swo | ||
|
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# Chip-ID file for L496x/L4A6x | ||
# Chip-ID file for STM32L496x / STM32L4A6x device | ||
# | ||
chip_id 0x461 | ||
description L496x/L4A6x | ||
flash_type 6 | ||
flash_pagesize 0x800 | ||
sram_size 0x40000 | ||
dev_type STM32L496x_L4A6x | ||
ref_manual_id 0351 | ||
chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x800 // 2 KB | ||
sram_size 0x40000 // 256 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 | ||
option_base 0x1fff7800 | ||
option_size 0x4 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE | ||
option_size 0x4 // 4 B | ||
flags swo | ||
|
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@@ -1,13 +1,14 @@ | ||
# Chip-ID file for L4Px | ||
# Chip-ID file for STM32L4Px device | ||
# | ||
chip_id 0x471 | ||
description L4Px | ||
flash_type 6 | ||
flash_pagesize 0x1000 | ||
sram_size 0xa0000 | ||
dev_type STM32L4Px | ||
ref_manual_id 0432 | ||
chip_id 0x471 // STLINK_CHIPID_STM32_L4PX | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x1000 // 4 KB | ||
sram_size 0xa0000 // 640 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags dualbank swo | ||
|
||
flags swo |
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# Chip-ID file for L4Rx | ||
# Chip-ID file for STM32L4Rx device | ||
# | ||
chip_id 0x470 | ||
description L4Rx | ||
flash_type 6 | ||
flash_pagesize 0x1000 | ||
sram_size 0xa0000 | ||
dev_type STM32L4Rx | ||
ref_manual_id 0432 | ||
chip_id 0x470 // STLINK_CHIPID_STM32_L4RX | ||
flash_type 6 // STLINK_FLASH_TYPE_L4 | ||
flash_size_reg 0x1fff75e0 | ||
flash_pagesize 0x1000 // 4 KB | ||
sram_size 0xa0000 // 640 KB | ||
bootrom_base 0x1fff0000 | ||
bootrom_size 0x7000 | ||
bootrom_size 0x7000 // 28 KB | ||
option_base 0x0 | ||
option_size 0x0 | ||
flags dualbank swo | ||
|
||
flags swo |
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