Merge pull request #501 from geoffreymbrown/stm32l432support

stm32l432 support
stlink-org · Oct 15, 2016 · f80412c · f80412c
2 parents 2e50937 + 9705248
commit f80412c
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Showing 4 changed files with 24 additions and 3 deletions.
diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h
@@ -34,6 +34,7 @@ enum stlink_stm32_chipids {
 	STLINK_CHIPID_STM32_F37x             = 0x432,
 	STLINK_CHIPID_STM32_F4_DE            = 0x433,
 	STLINK_CHIPID_STM32_F4_DSI           = 0x434,
+	STLINK_CHIPID_STM32_L43X             = 0x435,
 	/*
 	* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
 	* and some that are called "High".  0x427 is assigned to the other "Medium-

diff --git a/src/chipid.c b/src/chipid.c
@@ -406,6 +406,22 @@ static const struct stlink_chipid_params devices[] = {
             .bootrom_base = 0x1fff0000,      // Tables 4-6, pages 80-81 (Bank 1 system memory)
             .bootrom_size = 0x7000           // 28k (per bank), same source as base
         },
+	        {
+            // 	STLINK_CHIPID_STM32_L43X   
+            // From RM0392.
+ 	    .chip_id = STLINK_CHIPID_STM32_L43X,   
+            .description = "L43x device",
+            .flash_type = STLINK_FLASH_TYPE_L4,
+            .flash_size_reg = 0x1fff75e0,    // "Flash size data register" (sec 43.2, page 1410)
+            .flash_pagesize = 0x800,         // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76)
+            // SRAM1 is "up to" 64k in the standard Cortex-M memory map;
+            // SRAM2 is 16k mapped at at 0x10000000 (sec 2.3, page 73 for
+            // sizes; table 2, page 74 for SRAM2 location)
+            .sram_size = 0xc000,
+            .bootrom_base = 0x1fff0000,      // Tables 4-6, pages 80-81 (Bank 1 system memory)
+            .bootrom_size = 0x7000           // 28k (per bank), same source as base
+        },
+
 
  };
 

diff --git a/src/common.c b/src/common.c
@@ -1417,7 +1417,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
         unlock_flash_if(sl);
 
         /* select the page to erase */
-        if (sl->chip_id == STLINK_CHIPID_STM32_L4) {
+        if (sl->chip_id == STLINK_CHIPID_STM32_L4 || sl->chip_id == STLINK_CHIPID_STM32_L43X) {
             // calculate the actual bank+page from the address
             uint32_t page = calculate_L4_page(sl, flashaddr);
 
@@ -1767,7 +1767,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
         unlock_flash_if(sl);
 
         /* TODO: Check that Voltage range is 2.7 - 3.6 V */
-        if (sl->chip_id != STLINK_CHIPID_STM32_L4) {
+        if ((sl->chip_id != STLINK_CHIPID_STM32_L4) &&
+	    (sl->chip_id != STLINK_CHIPID_STM32_L43X))
+	  {
             if( sl->version.stlink_v == 1 ) {
                 printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n");
                 write_flash_cr_psiz(sl, 2);

diff --git a/src/flash_loader.c b/src/flash_loader.c
@@ -246,7 +246,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
     } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) {
         loader_code = loader_code_stm32f0;
         loader_size = sizeof(loader_code_stm32f0);
-    } else if (sl->chip_id == STLINK_CHIPID_STM32_L4) {
+    } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
+	       (sl->chip_id == STLINK_CHIPID_STM32_L43X))
+      {
         loader_code = loader_code_stm32l4;
         loader_size = sizeof(loader_code_stm32l4);
     } else {