[refactoring] sourcefile 'common.c'

CMakeLists.txt

@@ -2,7 +2,7 @@
 # General cmake settings
 ###
 
-cmake_minimum_required(VERSION 3.10.2)
+cmake_minimum_required(VERSION 3.7.2)
 cmake_policy(SET CMP0042 NEW)
 set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules)
 set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
@@ -110,6 +110,8 @@ add_subdirectory(inc)
 set(STLINK_HEADERS
         inc/backend.h
         inc/stlink.h
+        src/common_flash.h
+        src/calculate.h
         src/stlink-lib/commands.h
         src/stlink-lib/libusb_settings.h
         src/stlink-lib/reg.h
@@ -123,7 +125,13 @@ set(STLINK_HEADERS
         )
 
 set(STLINK_SOURCE
+        src/read_write.c
         src/common.c
+		    src/option.c
+		    src/common_flash.c
+        src/map_file.c
+        src/flashloader.c
+        src/calculate.c
         src/stlink-lib/chipid.c
         src/stlink-lib/flash_loader.c
         src/stlink-lib/logging.c

inc/stlink.h

@@ -1,3 +1,4 @@
+
 /*
  * File: stlink.h
  *
@@ -13,6 +14,7 @@
 #include <stdbool.h>
 
 #include "stm32.h"
+#include "stm32flash.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -284,15 +286,15 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_
 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
 
-int stlink_chip_id(stlink_t *sl, uint32_t *chip_id);
+//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id);
 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
 
 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
 int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size);
 int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr);
 uint16_t read_uint16(const unsigned char *c, const int pt);
-void stlink_core_stat(stlink_t *sl);
+//void stlink_core_stat(stlink_t *sl);
 void stlink_print_data(stlink_t *sl);
 unsigned int is_bigendian(void);
 uint32_t read_uint32(const unsigned char *c, const int pt);

inc/stm32.h

@@ -35,4 +35,44 @@
 #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
 #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
 
+#define STM32F0_DBGMCU_CR 0xE0042004
+#define STM32F0_DBGMCU_CR_IWDG_STOP 8
+#define STM32F0_DBGMCU_CR_WWDG_STOP 9
+
+#define STM32F4_DBGMCU_APB1FZR1 0xE0042008
+#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11
+#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12
+
+#define STM32L0_DBGMCU_APB1_FZ 0x40015808
+#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11
+#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12
+
+#define STM32H7_DBGMCU_APB1HFZ 0x5C001054
+#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18
+
+#define STM32WB_DBGMCU_APB1FZR1 0xE004203C
+#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11
+#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12
+
+#define STM32F1_RCC_AHBENR 0x40021014
+#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
+
+#define STM32F4_RCC_AHB1ENR 0x40023830
+#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN
+
+#define STM32G0_RCC_AHBENR 0x40021038
+#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
+
+#define STM32G4_RCC_AHB1ENR 0x40021048
+#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
+
+#define STM32L0_RCC_AHBENR 0x40021030
+#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN
+
+#define STM32H7_RCC_AHB1ENR 0x58024538
+#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
+
+#define STM32WB_RCC_AHB1ENR 0x58000048
+#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
+
 #endif // STM32_H