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Fixed flash, dbgmcu and rcc registers for STM32L1 #1266

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merged 1 commit into from
Aug 26, 2022

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trabucayre
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stm32 l0 and l1 shares most of the required registers address. But there is some small differences:

  • DBGMCU_APB1_FZ, RCC_AHBENR have differents address
  • l1 have less FLASH_SR error bits

This PR add some tests based on flash's base address when distinction is required between l0 and l1.

@Nightwalker-87 Nightwalker-87 added this to the v1.7.1 milestone Aug 26, 2022
@Nightwalker-87 Nightwalker-87 changed the title stm32l1: fix flash, dbgmcu and rcc registers Fixed flash, dbgmcu and rcc registers for STM32L1 Aug 26, 2022
@Nightwalker-87 Nightwalker-87 merged commit 3c258a1 into stlink-org:develop Aug 26, 2022
@stlink-org stlink-org locked as resolved and limited conversation to collaborators Aug 27, 2022
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3 participants