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Write and erase flash when the Internal RC Oscillator is off #1348

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vanrein
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@vanrein vanrein commented Oct 24, 2023

  • By first enabling it
  • This worked for me on STM32F103
  • Quite likely not the best structure
  • Willing to take instructions, or hand it over

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vanrein commented Oct 24, 2023

According to RM0008, the Reference Manual to STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm®-based 32-bit MCUs:

For write and erase operations on the Flash memory (write/erase), the internal RC oscillator
(HSI) must be ON.

You can imagine that I only found this after I had landed in a cyclical dependency; after every reboot the HSI would be off and so I could not flash a new program into the device. This fix remedied that. I think it makes life more robust, can hardly cause trouble (as we usually reset after a rewrite) and is a pleasant thing to have arranged quietly.

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vanrein commented Oct 24, 2023

I suspect that you have strict ideas about the program structure, and want it done elsewhere. I'm listening. I suppose the RCC_CR and its HSION bit also needs location on all devices. Perhaps in the .chip files?

Guidance is welcomed, but chances are you'll be faster off doing this yourself. Which is then kindly welcomed :-)

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vanrein commented Oct 24, 2023

FWIW, the code in action:

2023-10-24T21:50:34 DEBUG read_write.c: *** stlink_read_debug32  0x00035280 at 0x40021000
2023-10-24T21:50:34 DEBUG read_write.c: *** stlink_write_debug32 0x00035281 to 0x40021000
2023-10-24T21:50:34 DEBUG read_write.c: *** stlink_read_debug32  0x00035283 at 0x40021000

Reading the HSION in bit0 and HSIRDY in bit1, setting it in the next write, and reading the HSION/HSIRDY as both set in the subsequent read.

- By first enabling it
- This worked for me on STM32F103
- Quite likely not the best structure
- Willing to take instructions, or hand it over

Fixed the check to include HSIRDY alongside HSION
- When writing HSION, the HSIRDY takes some time to come up
- This may in theory have delays
- It is entirely proper to check the bits together; they are "ist & soll"
@Ant-ON
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Ant-ON commented Oct 25, 2023

@vanrein

According to RM0008, 7.2.6 System clock (SYSCLK) selection:

After a system reset, the HSI oscillator is selected as system clock.

How is the system clocked after a reset if the HSI is turned off?
Are you using connection under reset?

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vanrein commented Oct 26, 2023 via email

@Ant-ON
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Ant-ON commented Oct 26, 2023

@vanrein Hi, Rick!

I understood the situation. Thanks for the explanation!

The connect under reset option also performs a soft reset with halt (AIRCR_SYSRESETREQ with DEMCR_VC_CORERESET). Perhaps soft reset will solve the problem. Can you check this (--connect-under-reset option)?

Calling the reset function:
https://github.com/stlink-org/stlink/blob/31c7fc6f8aa8f55a9e3ab4b0a73d6d310b2bb212/src/stlink-lib/common.c#L1074C4

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vanrein commented Oct 27, 2023

Tried with st-flash --debug --reset on 31c7fc6 and fails. There are two ways it does this; instant response, and getting stuck; both shown below; it seems to be remaining state in the MCU, as power cycling the ST Link v2 + MCU remedies it; in general, the behaviour is unstable.

Returning to my patch e5be102 and power cycling to remove the other version's impact and flashing is stable.

st-flash 1.7.0-316-g31c7fc6-dirty
2023-10-27T13:53:32 DEBUG common.c: *** looking up stlink version ***
2023-10-27T13:53:32 DEBUG common.c: st vid         = 0x0483 (expect 0x0483)
2023-10-27T13:53:32 DEBUG common.c: stlink pid     = 0x3748
2023-10-27T13:53:32 DEBUG common.c: stlink version = 0x2
2023-10-27T13:53:32 DEBUG common.c: jtag version   = 0x1d
2023-10-27T13:53:32 DEBUG common.c: swim version   = 0x7
2023-10-27T13:53:32 DEBUG common.c: stlink current mode: mass
2023-10-27T13:53:32 DEBUG usb.c: JTAG/SWD freq set to 0
2023-10-27T13:53:32 DEBUG common.c: stlink current mode: mass
2023-10-27T13:53:32 DEBUG common.c: *** stlink_enter_swd_mode ***
2023-10-27T13:53:32 DEBUG usb.c: ENTER_SWD wait error (0x14), delaying 1000 us and retry
2023-10-27T13:53:32 DEBUG usb.c: ENTER_SWD wait error (0x14), delaying 2000 us and retry
2023-10-27T13:53:32 DEBUG usb.c: ENTER_SWD wait error (0x14), delaying 4000 us and retry
2023-10-27T13:53:32 DEBUG usb.c: ENTER_SWD wait error (0x14)
Failed to enter SWD mode
Failed to connect to target
Failed to parse flash type or unrecognized flash type
2023-10-27T13:53:32 DEBUG common.c: *** stlink_exit_debug_mode ***
2023-10-27T13:53:32 DEBUG common.c: *** stlink_close ***
ERROR: Flashing failed

This is virtually instant. Sometimes it gets stuck waiting infinitely for an OK:

st-flash 1.7.0-316-g31c7fc6-dirty
2023-10-27T13:55:29 DEBUG common.c: *** looking up stlink version ***
2023-10-27T13:55:29 DEBUG common.c: st vid         = 0x0483 (expect 0x0483)
2023-10-27T13:55:29 DEBUG common.c: stlink pid     = 0x3748
2023-10-27T13:55:29 DEBUG common.c: stlink version = 0x2
2023-10-27T13:55:29 DEBUG common.c: jtag version   = 0x1d
2023-10-27T13:55:29 DEBUG common.c: swim version   = 0x7
2023-10-27T13:55:29 DEBUG common.c: stlink current mode: dfu
2023-10-27T13:55:29 DEBUG usb.c: -- exit_dfu_mode
2023-10-27T13:55:29 DEBUG usb.c: JTAG/SWD freq set to 0
2023-10-27T13:55:30 DEBUG common.c: stlink current mode: mass
2023-10-27T13:55:30 DEBUG common.c: *** stlink_enter_swd_mode ***
2023-10-27T13:55:30 DEBUG common.c: Loading device parameters....
2023-10-27T13:55:30 DEBUG common.c: *** stlink_core_id ***
2023-10-27T13:55:30 DEBUG common.c: core_id = 0x1ba01477
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x411fc231 at 0xe000ed00
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x20036410 at 0xe0042000
2023-10-27T13:55:30 DEBUG chipid.c: detected chip_id parameters

2023-10-27T13:55:30 DEBUG chipid.c: # Device Type: STM32F1xx_MD
2023-10-27T13:55:30 DEBUG chipid.c: # Reference Manual: RM0008
2023-10-27T13:55:30 DEBUG chipid.c: #
2023-10-27T13:55:30 DEBUG chipid.c: chip_id 0x410
2023-10-27T13:55:30 DEBUG chipid.c: flash_type 1
2023-10-27T13:55:30 DEBUG chipid.c: flash_size_reg 0x1ffff7e0
2023-10-27T13:55:30 DEBUG chipid.c: flash_pagesize 0x400
2023-10-27T13:55:30 DEBUG chipid.c: sram_size 0x5000
2023-10-27T13:55:30 DEBUG chipid.c: bootrom_base 0x1ffff000
2023-10-27T13:55:30 DEBUG chipid.c: bootrom_size 0x800
2023-10-27T13:55:30 DEBUG chipid.c: option_base 0x1ffff800
2023-10-27T13:55:30 DEBUG chipid.c: option_size 0x10
2023-10-27T13:55:30 DEBUG chipid.c: flags 2

2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0xffff0040 at 0x1ffff7e0
2023-10-27T13:55:30 INFO common.c: STM32F1xx_MD: 20 KiB SRAM, 64 KiB flash in at least 1 KiB pages.
2023-10-27T13:55:30 DEBUG common.c: *** stlink_force_debug_mode ***
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0000000000 at 0xe0042004
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0x00000300 to 0xe0042004
2023-10-27T13:55:30 DEBUG common.c: *** stlink_status ***
2023-10-27T13:55:30 DEBUG usb.c: core status: 03030003
2023-10-27T13:55:30 DEBUG common.c:   core status: halted
file conssend.bin md5 checksum: 3b1dbc54370eabeab60969eb54fcb, stlink checksum: 0x0018a8f3
2023-10-27T13:55:30 INFO common_flash.c: Attempting to write 14376 (0x3828) bytes to stm32 address: 134217728 (0x8000000)
2023-10-27T13:55:30 DEBUG common.c: *** stlink_core_id ***
2023-10-27T13:55:30 DEBUG common.c: core_id = 0x1ba01477
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0000000000 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0x00000014 to 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000080 at 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0x45670123 to 0x40022004
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0xcdef89ab to 0x40022004
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0000000000 at 0x40022010
2023-10-27T13:55:30 DEBUG common_flash.c: Successfully unlocked flash
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0000000000 at 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0000000000 to 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0000000000 at 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0x00000002 to 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0x08000000 to 0x40022014
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000002 at 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_write_debug32 0x00000042 to 0x40022010
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c
2023-10-27T13:55:30 DEBUG read_write.c: *** stlink_read_debug32  0x00000003 at 0x4002200c

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vanrein commented Oct 27, 2023

I've been wondering why I ran into this, after so many others apparently have not. It may be because I'm avoiding the Cube software, because its license bans cross-MCU inclusion, and also because I prefer doing it without HAL and completely with arm-none-eabi-gcc. That makes it rare, but not dramatically so ;-)

My code is public, and these are the relevant portions:

@Ant-ON
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Ant-ON commented Oct 28, 2023

@vanrein
--reset it's another function. To check you need to run: st-flash --debug --reset --connect-under-reset

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vanrein commented Nov 7, 2023 via email

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I can't make out the point of general interest here, sry.

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Closing this ticket as there appears to be no general need and/or interest in this topic.

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