Breakpoint handling for Cortex M7 #341
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texane
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Breakpoint handling for Cortex M7
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This pull request uses chip_id to integrate the breakpoint handling for M7 targets into the handling of M0/1/3/4 breakpoints. The number of hardware breakpoints is not fixed by a define but read from the FP_CTRL register.
Tested on the STM32F746 Discovery, but must be tested on other targets before commited into main.
(Closes #266, Closes #273)