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Added STM32F413 parameters and verified with st-info and st-flash tools #549

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Jan 30, 2017
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3 changes: 2 additions & 1 deletion include/stlink/chipid.h
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,8 @@ enum stlink_stm32_chipids {
STLINK_CHIPID_STM32_F0_CAN = 0x448,
STLINK_CHIPID_STM32_F7 = 0x449,
STLINK_CHIPID_STM32_F7XXXX = 0x451,
STLINK_CHIPID_STM32_F410 = 0x458
STLINK_CHIPID_STM32_F410 = 0x458,
STLINK_CHIPID_STM32_F413 = 0x463
};

/**
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12 changes: 12 additions & 0 deletions src/chipid.c
Original file line number Diff line number Diff line change
Expand Up @@ -298,6 +298,18 @@ static const struct stlink_chipid_params devices[] = {
.bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4
.bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4
},
{
// RM0430 DocID029473 Rev 2 document was used to find these parameters
// Figure 2, Table 4, Table 5, Section 35.2
.chip_id = STLINK_CHIPID_STM32_F413,
.description = "F4 device",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2
.flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest)
.sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000)
.bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4
.bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4
},
{
.chip_id = STLINK_CHIPID_STM32_F09X,
.description = "F09X device",
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1 change: 1 addition & 0 deletions src/flash_loader.c
Original file line number Diff line number Diff line change
Expand Up @@ -219,6 +219,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
sl->chip_id == STLINK_CHIPID_STM32_F410 ||
sl->chip_id == STLINK_CHIPID_STM32_F411RE ||
sl->chip_id == STLINK_CHIPID_STM32_F412 ||
sl->chip_id == STLINK_CHIPID_STM32_F413 ||
sl->chip_id == STLINK_CHIPID_STM32_F446
) {
if( sl->version.stlink_v == 1 ) {
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