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Add support for G031/G041 chips. #825

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merged 2 commits into from
Mar 16, 2020
Merged

Add support for G031/G041 chips. #825

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f5d0454
Hotfix: Reverts commit 6692fdc.
Nightwalker-87 Feb 27, 2020
85d33b2
Merge branch 'master' into stlink_g0_soic8
Nightwalker-87 Mar 15, 2020
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2 changes: 2 additions & 0 deletions include/stlink/chipid.h
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Expand Up @@ -75,6 +75,8 @@ enum stlink_stm32_chipids {
STLINK_CHIPID_STM32_G4_CAT2 = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code".
STLINK_CHIPID_STM32_G4_CAT3 = 0x469,
STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board
STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G031/041
STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G071/081
STLINK_CHIPID_STM32_WB55 = 0x495
};

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1 change: 0 additions & 1 deletion include/stm32.h
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Expand Up @@ -9,7 +9,6 @@

// cortex core ids
#define STM32VL_CORE_ID 0x1ba01477
#define CS32VL_CORE_ID 0x2ba01477
#define STM32F7_CORE_ID 0x5ba02477

// Constant STM32 memory map figures
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2 changes: 1 addition & 1 deletion src/common.c
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Expand Up @@ -2637,7 +2637,7 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l

/* Check if chip is supported and for correct address */
if(sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 &&
sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) {
sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) {
ELOG("Option bytes writing is currently only supported for the STM32G0\n");
return -1;
}
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1 change: 0 additions & 1 deletion src/flash_loader.c
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Expand Up @@ -267,7 +267,6 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
loader_code = loader_code_stm32l;
loader_size = sizeof(loader_code_stm32l);
} else if (sl->core_id == STM32VL_CORE_ID ||
sl->core_id == CS32VL_CORE_ID ||
sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM ||
sl->chip_id == STLINK_CHIPID_STM32_F3 ||
sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL ||
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