stm32g4 chips update

[grevaillot]

• Add id and infos for stm32g47/48 chips.
• Update comments regarding g43/g44

I followed current g43x scheme of considering sram1/sram2/ccm sram as contiguous, but documented it.

Note that I've only worked with the first of the two banks. stm32g474 can also be configured as a single 512kb bank, with 4k pages via option bytes. but i think there's no logic to handle that properly ?

[Nightwalker-87]

Thank you for keeping this up to date.
We shall have some additional testing here...
As I can't help out here due to missing hardware, we should ask the community for assistance.
Maybe someone also has an idea regarding your note.

[Nightwalker-87]

Note that I've only worked with the first of the two banks. stm32g474 can also be configured as a single 512kb bank, with 4k pages via option bytes. but i think there's no logic to handle that properly ?

Looking at this again and the respective datasheet (page 19) this would likely make use of the MCU's S-bus. If this should require option bytes to be set, we don't need to address this with this PR necessarily. I'm not familiar with this device though.

[Nightwalker-87]

@grevaillot How do you think about this?

[Nightwalker-87]

ping @grevaillot

[grevaillot]

i think that PR is okay as it. i'll push some enhanced support for Gx devices with option read/write and dynamic dual bank flash handling soom, in a new pr.

[Nightwalker-87]

Thanks!