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Basic compatibility for STLink-v3 programmer #954

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merged 8 commits into from
May 17, 2020
Merged

Basic compatibility for STLink-v3 programmer #954

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afaded2
General Project Update
Nightwalker-87 Feb 22, 2020
82ac538
Merge remote-tracking branch 'origin/master' into add_stlink_v3_support
martonmiklos Feb 23, 2020
09ea99a
Add support for STLink V3
martonmiklos Feb 24, 2020
0a91936
Merge remote-tracking branch 'upstream/develop' into add_stlink_v3_su…
martonmiklos Apr 22, 2020
442ade8
Merge branch 'add_stlink_v3_support' of git://github.com/martonmiklos…
Nightwalker-87 May 7, 2020
f6e9cb1
Additional fixes for #863
Nightwalker-87 May 9, 2020
d827ce1
Merge branch 'develop' into stlink-v3_pre
Nightwalker-87 May 9, 2020
def770b
Bugfix & cleanup
Nightwalker-87 May 17, 2020
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191 changes: 118 additions & 73 deletions include/stlink.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* File: stlink.h
* File: stlink.h
*
* This should contain all the common top level stlink interfaces,
* regardless of how the backend does the work....
Expand All @@ -20,73 +20,109 @@ extern "C" {

#define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))

// Max data transfer size.
/* Max data transfer size */
// 6kB = max mem32_read block, 8kB sram
//#define Q_BUF_LEN 96
#define Q_BUF_LEN (1024 * 100)
#define Q_BUF_LEN (1024 * 100)

// STLINK_DEBUG_RESETSYS, etc:
#define STLINK_CORE_RUNNING 0x80
#define STLINK_CORE_HALTED 0x81
#define STLINK_CORE_STAT_UNKNOWN -1
enum target_state {
TARGET_UNKNOWN = 0,
TARGET_RUNNING = 1,
TARGET_HALTED = 2,
TARGET_RESET = 3,
TARGET_DEBUG_RUNNING = 4,
};

#define STLINK_CORE_RUNNING 0x80
#define STLINK_CORE_HALTED 0x81

#define STLINK_GET_VERSION 0xf1
#define STLINK_GET_CURRENT_MODE 0xf5
#define STLINK_GET_TARGET_VOLTAGE 0xF7
#define STLINK_GET_VERSION 0xF1
#define STLINK_GET_CURRENT_MODE 0xF5
#define STLINK_GET_TARGET_VOLTAGE 0xF7

#define STLINK_DEBUG_COMMAND 0xF2
#define STLINK_DFU_COMMAND 0xF3
#define STLINK_DFU_EXIT 0x07
#define STLINK_DEBUG_COMMAND 0xF2
#define STLINK_DFU_COMMAND 0xF3
#define STLINK_DFU_EXIT 0x07

// STLINK_GET_CURRENT_MODE
#define STLINK_DEV_DFU_MODE 0x00
#define STLINK_DEV_MASS_MODE 0x01
#define STLINK_DEV_DEBUG_MODE 0x02
#define STLINK_DEV_UNKNOWN_MODE -1
#define STLINK_DEV_DFU_MODE 0x00
#define STLINK_DEV_MASS_MODE 0x01
#define STLINK_DEV_DEBUG_MODE 0x02
#define STLINK_DEV_UNKNOWN_MODE -1

// TODO - possible poor names...
#define STLINK_SWD_ENTER 0x30
#define STLINK_SWD_READCOREID 0x32 // TBD
#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
#define STLINK_JTAG_READDEBUG_32BIT 0x36
#define STLINK_JTAG_DRIVE_NRST 0x3c

#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43

#define STLINK_APIV3_SET_COM_FREQ 0x61
#define STLINK_APIV3_GET_COM_FREQ 0x62

#define STLINK_APIV3_GET_VERSION_EX 0xFB

// Baud rate divisors for SWDCLK
#define STLINK_SWDCLK_4MHZ_DIVISOR 0
#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1
#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2
#define STLINK_SWDCLK_950KHZ_DIVISOR 3
#define STLINK_SWDCLK_480KHZ_DIVISOR 7
#define STLINK_SWDCLK_240KHZ_DIVISOR 15
#define STLINK_SWDCLK_125KHZ_DIVISOR 31
#define STLINK_SWDCLK_100KHZ_DIVISOR 40
#define STLINK_SWDCLK_50KHZ_DIVISOR 79
#define STLINK_SWDCLK_25KHZ_DIVISOR 158
#define STLINK_SWDCLK_15KHZ_DIVISOR 265
#define STLINK_SWDCLK_5KHZ_DIVISOR 798

#define STLINK_SERIAL_MAX_SIZE 64
#define STLINK_SWD_ENTER 0x30
#define STLINK_SWD_READCOREID 0x32 // TBD
#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
#define STLINK_JTAG_READDEBUG_32BIT 0x36
#define STLINK_JTAG_DRIVE_NRST 0x3C

#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43

#define STLINK_APIV3_SET_COM_FREQ 0x61
#define STLINK_APIV3_GET_COM_FREQ 0x62

#define STLINK_APIV3_GET_VERSION_EX 0xFB

/* Baud rate divisors for SWDCLK */
#define STLINK_SWDCLK_4MHZ_DIVISOR 0
#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1
#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2
#define STLINK_SWDCLK_950KHZ_DIVISOR 3
#define STLINK_SWDCLK_480KHZ_DIVISOR 7
#define STLINK_SWDCLK_240KHZ_DIVISOR 15
#define STLINK_SWDCLK_125KHZ_DIVISOR 31
#define STLINK_SWDCLK_100KHZ_DIVISOR 40
#define STLINK_SWDCLK_50KHZ_DIVISOR 79
#define STLINK_SWDCLK_25KHZ_DIVISOR 158
#define STLINK_SWDCLK_15KHZ_DIVISOR 265
#define STLINK_SWDCLK_5KHZ_DIVISOR 798

#define STLINK_SERIAL_MAX_SIZE 64

#define STLINK_V3_MAX_FREQ_NB 10

/* Cortex Debug Control Block */
#define DCB_DHCSR 0xE000EDF0
#define DCB_DCRSR 0xE000EDF4
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC

/* DCB_DHCSR bit and field definitions */
#define DBGKEY (0xA05F << 16)
#define C_DEBUGEN (1 << 0)
#define C_HALT (1 << 1)
#define C_STEP (1 << 2)
#define C_MASKINTS (1 << 3)
#define S_REGRDY (1 << 16)
#define S_HALT (1 << 17)
#define S_SLEEP (1 << 18)
#define S_LOCKUP (1 << 19)
#define S_RETIRE_ST (1 << 24)
#define S_RESET_ST (1 << 25)

/* Map the relevant features, quirks and workaround for specific firmware version of stlink */
#define STLINK_F_HAS_TRACE (1<<0)
#define STLINK_F_HAS_SWD_SET_FREQ (1<<1)
#define STLINK_F_HAS_JTAG_SET_FREQ (1<<2)
#define STLINK_F_HAS_MEM_16BIT (1<<3)
#define STLINK_F_HAS_GETLASTRWSTATUS2 (1<<4)
#define STLINK_F_HAS_DAP_REG (1<<5)
#define STLINK_F_QUIRK_JTAG_DP_READ (1<<6)
#define STLINK_F_HAS_AP_INIT (1<<7)
#define STLINK_F_HAS_DPBANKSEL (1<<8)
#define STLINK_F_HAS_RW8_512BYTES (1<<9)

#define STLINK_V3_MAX_FREQ_NB 10


/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
#define C_BUF_LEN 32

enum stlink_flash_type {
STLINK_FLASH_TYPE_UNKNOWN = 0,
STLINK_FLASH_TYPE_F0, /* used by f0, f1 (except f1xl),f3. */
STLINK_FLASH_TYPE_F1_XL, /* f0 flash with dual bank, apparently */
STLINK_FLASH_TYPE_F4, /* used by f2, f4, f7 */
STLINK_FLASH_TYPE_L0, /* l0, l1 */
STLINK_FLASH_TYPE_L4, /* l4, l4+ */
STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */
STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */
STLINK_FLASH_TYPE_F4, // used by f2, f4, f7 */
STLINK_FLASH_TYPE_L0, // l0, l1 */
STLINK_FLASH_TYPE_L4, // l4, l4+ */
STLINK_FLASH_TYPE_G0,
STLINK_FLASH_TYPE_G4,
STLINK_FLASH_TYPE_WB
Expand All @@ -110,8 +146,8 @@ struct stlink_reg {
typedef uint32_t stm32_addr_t;

typedef struct flash_loader {
stm32_addr_t loader_addr; /* loader sram adddr */
stm32_addr_t buf_addr; /* buffer sram address */
stm32_addr_t loader_addr; // loader sram addr
stm32_addr_t buf_addr; // buffer sram address
} flash_loader_t;

typedef struct _cortex_m3_cpuid_ {
Expand All @@ -121,12 +157,22 @@ typedef struct _cortex_m3_cpuid_ {
uint8_t revision;
} cortex_m3_cpuid_t;

enum stlink_jtag_api_version {
STLINK_JTAG_API_V1 = 1,
STLINK_JTAG_API_V2,
STLINK_JTAG_API_V3,
};

typedef struct stlink_version_ {
uint32_t stlink_v;
uint32_t jtag_v;
uint32_t swim_v;
uint32_t st_vid;
uint32_t stlink_pid;
// jtag api version supported
enum stlink_jtag_api_version jtag_api;
// one bit for each feature supported. See macros STLINK_F_*
uint32_t flags;
} stlink_version_t;

enum transport_type {
Expand All @@ -136,8 +182,8 @@ enum transport_type {
TRANSPORT_TYPE_INVALID
};

typedef struct _stlink stlink_t;

typedef struct _stlink stlink_t;
#include <backend.h>

struct _stlink {
Expand All @@ -152,36 +198,35 @@ struct _stlink {

// transport layer verboseness: 0 for no debug info, 10 for lots
int verbose;
int opt; // set by main() in tools/flash.c, empty tail bytes drop optimization
uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID
uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram
int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx
int opt;
uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID
uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram
enum target_state core_stat; // set by stlink_status()

char serial[STLINK_SERIAL_MAX_SIZE];
int serial_size;
int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR

int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR

enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx
enum stlink_flash_type flash_type;
// stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx
bool has_dual_bank;

stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
size_t flash_size; // calculated by stlink_load_device_params()
size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params()
stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
size_t flash_size; // calculated by stlink_load_device_params()
size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params()

/* sram settings */
stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()
stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()

/* option settings */
stm32_addr_t option_base;
size_t option_size;

// bootloader
// sys_base and sys_size are not used by the tools, but are only there to
// download the bootloader code (see tests/sg.c)
stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params()
size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params()
// sys_base and sys_size are not used by the tools, but are only there to download the bootloader code (see tests/sg.c)
stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params()
size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params()

struct stlink_version_ version;
};
Expand Down
49 changes: 29 additions & 20 deletions include/stlink/commands.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,26 +2,35 @@
#define STLINK_COMMANDS_H_

enum stlink_debug_commands {
STLINK_DEBUG_ENTER_JTAG = 0x00,
STLINK_DEBUG_GETSTATUS = 0x01,
STLINK_DEBUG_FORCEDEBUG = 0x02,
STLINK_DEBUG_RESETSYS = 0x03,
STLINK_DEBUG_READALLREGS = 0x04,
STLINK_DEBUG_READREG = 0x05,
STLINK_DEBUG_WRITEREG = 0x06,
STLINK_DEBUG_READMEM_32BIT = 0x07,
STLINK_DEBUG_WRITEMEM_32BIT = 0x08,
STLINK_DEBUG_RUNCORE = 0x09,
STLINK_DEBUG_STEPCORE = 0x0a,
STLINK_DEBUG_SETFP = 0x0b,
STLINK_DEBUG_WRITEMEM_8BIT = 0x0d,
STLINK_DEBUG_CLEARFP = 0x0e,
STLINK_DEBUG_WRITEDEBUGREG = 0x0f,
STLINK_DEBUG_ENTER = 0x20,
STLINK_DEBUG_EXIT = 0x21,
STLINK_DEBUG_READCOREID = 0x22,
STLINK_DEBUG_APIV2_ENTER = 0x30,
STLINK_DEBUG_ENTER_SWD = 0xa3
STLINK_DEBUG_ENTER_JTAG = 0x00,
STLINK_DEBUG_GETSTATUS = 0x01,
STLINK_DEBUG_FORCEDEBUG = 0x02,
STLINK_DEBUG_APIV1_RESETSYS = 0x03,
STLINK_DEBUG_APIV1_READALLREGS = 0x04,
STLINK_DEBUG_APIV1_READREG = 0x05,
STLINK_DEBUG_APIV1_WRITEREG = 0x06,
STLINK_DEBUG_READMEM_32BIT = 0x07,
STLINK_DEBUG_WRITEMEM_32BIT = 0x08,
STLINK_DEBUG_RUNCORE = 0x09,
STLINK_DEBUG_STEPCORE = 0x0a,
STLINK_DEBUG_APIV1_SETFP = 0x0b,
STLINK_DEBUG_WRITEMEM_8BIT = 0x0d,
STLINK_DEBUG_APIV1_CLEARFP = 0x0e,
STLINK_DEBUG_APIV1_WRITEDEBUGREG = 0x0f,
STLINK_DEBUG_APIV1_ENTER = 0x20,
STLINK_DEBUG_EXIT = 0x21,
STLINK_DEBUG_READCOREID = 0x22,
STLINK_DEBUG_APIV2_ENTER = 0x30,
STLINK_DEBUG_APIV2_READ_IDCODES = 0x31,
STLINK_DEBUG_APIV2_RESETSYS = 0x32,
STLINK_DEBUG_APIV2_READREG = 0x33,
STLINK_DEBUG_APIV2_WRITEREG = 0x34,
STLINK_DEBUG_APIV2_WRITEDEBUGREG = 0x35,
STLINK_DEBUG_APIV2_READDEBUGREG = 0x36,
STLINK_DEBUG_APIV2_READALLREGS = 0x3A,
STLINK_DEBUG_APIV2_GETLASTRWSTATUS = 0x3B,
STLINK_DEBUG_APIV2_GETLASTRWSTATUS2 = 0x3E,
STLINK_DEBUG_ENTER_SWD = 0xa3
};

#endif /* STLINK_COMMANDS_H_ */