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USART1 connects to PCLK1. #260

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Jul 28, 2021
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4 changes: 4 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
features, can no longer be disabled. ([#259])
1. The "unproven" features are no longer unproven and used anywhere anyways.
2. This crate was not building successfully without the unproven feature.
- Set the correct baud rate for chips where `USART1SW_A::PCLK` leads to a
baud rate derived from PCLK1, rather than the ports own bus clock, PCLK2.
([#260])

### Breaking Changes

Expand Down Expand Up @@ -367,6 +370,7 @@ let clocks = rcc
[defmt]: https://github.com/knurling-rs/defmt
[filter]: https://defmt.ferrous-systems.com/filtering.html

[#260]: https://github.com/stm32-rs/stm32f3xx-hal/pull/260
[#259]: https://github.com/stm32-rs/stm32f3xx-hal/pull/259
[#257]: https://github.com/stm32-rs/stm32f3xx-hal/pull/257
[#255]: https://github.com/stm32-rs/stm32f3xx-hal/pull/255
Expand Down
18 changes: 16 additions & 2 deletions src/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -869,8 +869,22 @@ macro_rules! usart_var_clock {
}

cfg_if::cfg_if! {
if #[cfg(any(feature = "svd-f301", feature = "svd-f3x4"))] {
usart_var_clock!([(1,2)]);
if #[cfg(any(
feature = "stm32f301x6",
feature = "stm32f301x8",
feature = "stm32f318x8",
feature = "stm32f302x6",
feature = "stm32f302x8",
feature = "stm32f303x6",
feature = "stm32f303x8",
feature = "stm32f328x8",
feature = "stm32f334x4",
feature = "stm32f334x6",
feature = "stm32f334x8",
))] {
// USART1 is accessed through APB2,
// but USART1SW_A::PCLK will connect its phy to PCLK1.
usart_var_clock!([(1,1)]);
// These are uart peripherals, where the only clock source
// is the PCLK (peripheral clock).
usart_static_clock!([(2,1), (3,1)]);
Expand Down