✨ add support for RISC-V 'Zicond' ISA extension (#546)

CHANGELOG.md

@@ -31,6 +31,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 11.03.2023 | 1.8.2.2 | :sparkles: add support for RISC-V `Zicond` ISA extension (conditional operations); [#546](https://github.com/stnolting/neorv32/pull/546) |
 | 10.02.2023 | 1.8.2.1 | rtl code edits, clean-ups and minor optimizations (improve branch prediction); [#545](https://github.com/stnolting/neorv32/pull/545) |
 | 10.03.2023 | [**:rocket:1.8.2**](https://github.com/stnolting/neorv32/releases/tag/v1.8.2) | **New release** |
 | 09.03.2023 | 1.8.1.10 | :warning: move tri-state drivers (ONEWIRE and TWI) out of the core; [#543](https://github.com/stnolting/neorv32/pull/543) |

README.md

@@ -115,8 +115,9 @@ see the [_open-source architecture ID list_](https://github.com/riscv/riscv-isa-
 [[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
 [[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
 [[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
+[[`Zico`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
 [[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
-[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
+[[`Zicond`](https://stnolting.github.io/neorv32/#_zicond_conditional_operations_extension)]
 [[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
 [[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
 [[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
@@ -133,7 +134,7 @@ and *Privileged Architecture Specification* ([pdf](https://github.com/stnolting/
 * 16 fast interrupt request channels as NEORV32-specific extension
 * custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as `Zxcfu` ISA extension)
 for _custom RISC-V instructions_ (R3-type, R4-type and R5-type);
-* _intrinsic_ libraries for the `Zxcfu` and `Zfinx` ISA extensions
+* _intrinsic_ libraries for the `Zicond`, `Zfinx` and `Zxcfu` ISA extensions
 
 **Memories**
 

docs/datasheet/cpu.adoc

@@ -27,6 +27,7 @@ image::neorv32_cpu_block.png[width=600,align=center]
 ** `Zfinx` - single-precision floating-point unit
 ** `Zicsr` - control and status register access (privileged architecture)
 ** `Zicntr` - CPU base counters
+** `Zicond` - conditionaloperations
 ** `Zihpm` - hardware performance monitors
 ** `Zifencei` - instruction stream synchronization
 ** `Zmmul` - integer multiplication hardware
@@ -681,7 +682,22 @@ generic is _true_. It allows manual synchronization of the instruction stream vi
 The `fence.i` instruction resets the CPU's front-end (instruction fetch) and flushes the prefetch buffer.
 This allows a clean re-fetch of modified instructions from memory. Also, the top's `i_bus_fencei_o` signal is set
 high for one cycle to inform the memory system (like the i-cache to perform a flush/reload.
-Any additional flags within the `fence.i` instruction word are ignore by the hardware.
+Any additional flags within the `fence.i` instruction word are ignored by the hardware.
+
+
+==== **`Zicond`** Conditional Operations Extension
+
+The `Ziconds` ISa extension implements conditional operations ("move or set-tot-zero"). When enabled, to additional
+instructions are supported:
+
+* `czero.eqz` `czero.nez`
+
+Software can utilize the custom instructions by using _intrinsics_, which are basically inline assembly functions that
+behave like regular C functions but that evaluate to a single custom instruction word (not calling overhead at all).
+
+[WARNING]
+The `Zicond` extension is not ratified nor frozen yet. An intrinsic library is provided to utilize the `Zicond`
+conditional operations from C-language code (see `sw/example/zicond_test`).
 
 
 ==== **`Zxcfu`** Custom Instructions Extension (CFU)
@@ -810,22 +826,17 @@ configurations are presented in <<_cpu_performance>>.
 | Floating-point - conversion | `Zfinx` | `fcvt.w.s` `fcvt.wu.s` | 47
 | Floating-point - conversion | `Zfinx` | `fcvt.s.w` `fcvt.s.wu` | 48
 | Bit-manipulation - arithmetic/logic    | `B(Zbb)` | `min[u]` `max[u]` `sext.b` `sext.h` `andn` `orn` `xnor` `zext`(pack) `rev8`(grevi) `orc.b`(gorci) | 4
-| Bit-manipulation - shifts              | `B(Zbb)` | `clz` `ctz` | 4 + 1..32; FAST_SHIFT: 4
+| Bit-manipulation - shifts              | `B(Zbb)` | `clz` `ctz` | 4 + _shift_amount_; FAST_SHIFT: 4
 | Bit-manipulation - shifts              | `B(Zbb)` | `cpop` | 36; FAST_SHIFT: 4
 | Bit-manipulation - shifts              | `B(Zbb)` | `rol` `ror[i]` | 4 + _shift_amount_; FAST_SHIFT: 4
 | Bit-manipulation - shifted-add         | `B(Zba)` | `sh1add` `sh2add` `sh3add` | 4
 | Bit-manipulation - single-bit          | `B(Zbs)` | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 4
 | Bit-manipulation - carry-less multiply | `B(Zbc)` | `clmul` `clmulh` `clmulr` | 36
-| Custom instructions (CFU) | `Zxcfu` | - | _custom_ (min. 4)
-| | | | 
-| _Illegal instructions_    | `Zicsr` | - | 2
+| Conditional operations    | `Zicond` | `czero.eqz` `czero.nez` | 3
+| Custom instructions (CFU) | `Zxcfu` | user-defined | user-defined
+| _Illegal instructions_ | - | - | 2
 |=======================
 
-[NOTE]
-The presented values of the *floating-point execution cycles* are average values - obtained from
-4096 instruction executions using pseudo-random input values. The execution time for emulating the
-instructions (using pure-software libraries) is ~17..140 times higher.
-
 
 <<<
 // ####################################################################################################################

docs/datasheet/cpu_csr.adoc

@@ -852,21 +852,21 @@ discover ISA sub-extensions and CPU configuration options.
 [options="header",grid="rows"]
 |=======================
 | Bit   | Name [C] | R/W | Function
-| 31    | _CSR_MXISA_FASTSHIFT_ | r/- | fast shifts available when set (via top's <<_fast_shift_en>> generic)
-| 30    | _CSR_MXISA_FASTMUL_   | r/- | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
-| 31:21 | -                     | r/- | _reserved_, read as zero
-| 20    | _CSR_MXISA_IS_SIM_    | r/- | set if CPU is being **simulated** (⚠️ not guaranteed)
-| 19:11 | -                     | r/- | _reserved_, read as zero
-| 11    | _CSR_MXISA_SDTRIG_    | r/- | `Sdtrig` extension (trigger module) available when set (via top's <<_cpu_extension_riscv_sdtrig>> generic)
-| 10    | _CSR_MXISA_SDEXT_     | r/- | `Sdext` extension (debug mode) available when set (via top's <<_cpu_extension_riscv_sdext>> generic)
-|  9    | _CSR_MXISA_ZIHPM_     | r/- | `Zihpm` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
-|  8    | _CSR_MXISA_PMP_       | r/- | `PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
-|  7    | _CSR_MXISA_ZICNTR_    | r/- | `Zicntr` extension (`I` sub-extension) available when set - `[m]cycle` and `[m]instret` CSRs available when set (via top's <<_cpu_extension_riscv_zicntr>> generic)
-|  6    | -                     | r/- | _reserved_, read as zero
-|  5    | _CSR_MXISA_ZFINX_     | r/- | `Zfinx` extension (`F` sub-/alternative-extension: FPU using `x` registers) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
-|  4    | -                     | r/- | _reserved_, read as zero
-|  3    | _CSR_MXISA_ZXCFU_     | r/- | `Zxcfu` extension (custom functions unit for custom RISC-V instructions) available when set (via top's <<_cpu_extension_riscv_zxcfu>> generic)
-|  2    | _CSR_MXISA_ZMMUL_     | r/- | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
-|  1    | _CSR_MXISA_ZIFENCEI_  | r/- | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
 |  0    | _CSR_MXISA_ZICSR_     | r/- | `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
+|  1    | _CSR_MXISA_ZIFENCEI_  | r/- | `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
+|  2    | _CSR_MXISA_ZMMUL_     | r/- | `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
+|  3    | _CSR_MXISA_ZXCFU_     | r/- | `Zxcfu` extension (custom functions unit for custom RISC-V instructions) available when set (via top's <<_cpu_extension_riscv_zxcfu>> generic)
+|  4    | _CSR_MXISA_ZICOND_    | r/- | `Zicond` extension (conditional operations) available when set (via top's <<_cpu_extension_riscv_zicond>> generic)
+|  5    | _CSR_MXISA_ZFINX_     | r/- | `Zfinx` extension (`F` sub-/alternative-extension: FPU using `x` registers) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
+|  6    | -                     | r/- | _reserved_, read as zero
+|  7    | _CSR_MXISA_ZICNTR_    | r/- | `Zicntr` extension (`I` sub-extension) available when set - `[m]cycle` and `[m]instret` CSRs available when set (via top's <<_cpu_extension_riscv_zicntr>> generic)
+|  8    | _CSR_MXISA_PMP_       | r/- | `PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
+|  9    | _CSR_MXISA_ZIHPM_     | r/- | `Zihpm` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
+| 10    | _CSR_MXISA_SDEXT_     | r/- | `Sdext` extension (debug mode) available when set (via top's <<_cpu_extension_riscv_sdext>> generic)
+| 11    | _CSR_MXISA_SDTRIG_    | r/- | `Sdtrig` extension (trigger module) available when set (via top's <<_cpu_extension_riscv_sdtrig>> generic)
+| 19:12 | -                     | r/- | _reserved_, read as zero
+| 20    | _CSR_MXISA_IS_SIM_    | r/- | set if CPU is being **simulated** (⚠️ not guaranteed)
+| 31:21 | -                     | r/- | _reserved_, read as zero
+| 30    | _CSR_MXISA_FASTMUL_   | r/- | fast multiplication available when set (via top's <<_fast_mul_en>> generic)
+| 31    | _CSR_MXISA_FASTSHIFT_ | r/- | fast shifts available when set (via top's <<_fast_shift_en>> generic)
 |=======================

docs/datasheet/overview.adoc

@@ -76,7 +76,7 @@ include::rationale.adoc[]
 
 * 32-bit `rv32i` RISC-V CPU
 * fully RISC-V ISA compatible - checked by the https://github.com/stnolting/neorv32-riscof[official RISCOF architecture tests]
-* base ISA + privileged ISA (optional) + several ISA extensions (optional)
+* base ISA + privileged ISA + several optional standard and custom ISA extensions
 * option to add custom RISC-V instructions as custom ISA extension
 * rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
 * aims to support <<_full_virtualization>> capabilities to increase execution safety
@@ -184,7 +184,8 @@ neorv32_top.vhd                  - NEORV32 Processor top entity
 ├neorv32_cpu.vhd                 - NEORV32 CPU top entity
 │├neorv32_cpu_alu.vhd            - Arithmetic/logic unit
 ││├neorv32_cpu_cp_bitmanip.vhd   - Bit-manipulation co-processor (B ext.)
-││├neorv32_cpu_cp_cfu.vhd        - Custom functions (instruction) co-processor (Zxcfu ext.)
+││├neorv32_cpu_cp_cfu.vhd        - Custom instructions co-processor (Zxcfu ext.)
+││├neorv32_cpu_cp_cond.vhd       - Conditional operations co-processor (Zicond ext.)
 ││├neorv32_cpu_cp_fpu.vhd        - Floating-point co-processor (Zfinx ext.)
 ││├neorv32_cpu_cp_muldiv.vhd     - Mul/Div co-processor (M ext.)
 ││└neorv32_cpu_cp_shifter.vhd    - Bit-shift co-processor (base ISA)
@@ -261,8 +262,6 @@ just _exemplary_. If not otherwise mentioned all implementations use the default
 [options="header",grid="rows"]
 |=======================
 | CPU ISA Configuration                             | LEs  | FFs  | MEM bits | DSPs | _f~max~_
-| `rv32e`                                           |  720 |  360 |      512 |    0 | 130 MHz
-| `rv32i`                                           |  724 |  364 |     1024 |    0 | 130 MHz
 | `rv32i_Zicsr`                                     | 1223 |  607 |     1024 |    0 | 130 MHz
 | `rv32i_Zicsr_Zicntr`                              | 1578 |  773 |     1024 |    0 | 130 MHz
 | `rv32im_Zicsr_Zicntr`                             | 2087 |  983 |     1024 |    0 | 130 MHz

docs/datasheet/soc.adoc

@@ -365,6 +365,17 @@ See section <<_zicntr_cpu_base_counters>> for more information.
 |======
 
 
+:sectnums!:
+===== _CPU_EXTENSION_RISCV_Zicond_
+
+[cols="4,4,2"]
+[frame="all",grid="none"]
+|======
+| **CPU_EXTENSION_RISCV_Zicond** | _boolean_ | false
+3+| Implement the <<_zicond_conditional_operations_extension>> ISA extension when true.
+|======
+
+
 :sectnums!:
 ===== _CPU_EXTENSION_RISCV_Zihpm_
 

rtl/core/neorv32_cpu.vhd

@@ -55,6 +55,7 @@ entity neorv32_cpu is
     CPU_EXTENSION_RISCV_Zfinx    : boolean; -- implement 32-bit floating-point extension (using INT reg!)
     CPU_EXTENSION_RISCV_Zicsr    : boolean; -- implement CSR system?
     CPU_EXTENSION_RISCV_Zicntr   : boolean; -- implement base counters?
+    CPU_EXTENSION_RISCV_Zicond   : boolean; -- implement conditional operations extension?
     CPU_EXTENSION_RISCV_Zihpm    : boolean; -- implement hardware performance monitors?
     CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
     CPU_EXTENSION_RISCV_Zmmul    : boolean; -- implement multiply-only M sub-extension?
@@ -171,9 +172,10 @@ begin
     cond_sel_string_f(CPU_EXTENSION_RISCV_U,        "U", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr,    "_Zicsr", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Zicntr,   "_Zicntr", "") &
-    cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm,    "_Zihpm", "") &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zicond,   "_Zicond", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx,    "_Zfinx", "") &
+    cond_sel_string_f(CPU_EXTENSION_RISCV_Zihpm,    "_Zihpm", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul,    "_Zmmul", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Zxcfu,    "_Zxcfu", "") &
     cond_sel_string_f(CPU_EXTENSION_RISCV_Sdext,    "_Sdext", "") &
@@ -271,6 +273,7 @@ begin
     CPU_EXTENSION_RISCV_Zfinx    => CPU_EXTENSION_RISCV_Zfinx,    -- implement 32-bit floating-point extension (using INT reg!)
     CPU_EXTENSION_RISCV_Zicsr    => CPU_EXTENSION_RISCV_Zicsr,    -- implement CSR system?
     CPU_EXTENSION_RISCV_Zicntr   => CPU_EXTENSION_RISCV_Zicntr,   -- implement base counters?
+    CPU_EXTENSION_RISCV_Zicond   => CPU_EXTENSION_RISCV_Zicond,   -- implement conditional operations extension?
     CPU_EXTENSION_RISCV_Zihpm    => CPU_EXTENSION_RISCV_Zihpm,    -- implement hardware performance monitors?
     CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
     CPU_EXTENSION_RISCV_Zmmul    => CPU_EXTENSION_RISCV_Zmmul,    -- implement multiply-only M sub-extension?
@@ -374,16 +377,17 @@ begin
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_alu_inst: neorv32_cpu_alu
   generic map (
-    XLEN                      => XLEN,                      -- data path width
+    XLEN                       => XLEN,                       -- data path width
     -- RISC-V CPU Extensions --
-    CPU_EXTENSION_RISCV_B     => CPU_EXTENSION_RISCV_B,     -- implement bit-manipulation extension?
-    CPU_EXTENSION_RISCV_M     => CPU_EXTENSION_RISCV_M,     -- implement mul/div extension?
-    CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
-    CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
-    CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
+    CPU_EXTENSION_RISCV_B      => CPU_EXTENSION_RISCV_B,      -- implement bit-manipulation extension?
+    CPU_EXTENSION_RISCV_M      => CPU_EXTENSION_RISCV_M,      -- implement mul/div extension?
+    CPU_EXTENSION_RISCV_Zmmul  => CPU_EXTENSION_RISCV_Zmmul,  -- implement multiply-only M sub-extension?
+    CPU_EXTENSION_RISCV_Zfinx  => CPU_EXTENSION_RISCV_Zfinx,  -- implement 32-bit floating-point extension (using INT reg!)
+    CPU_EXTENSION_RISCV_Zxcfu  => CPU_EXTENSION_RISCV_Zxcfu,  -- implement custom (instr.) functions unit?
+    CPU_EXTENSION_RISCV_Zicond => CPU_EXTENSION_RISCV_Zicond, -- implement conditional operations extension?
     -- Extension Options --
-    FAST_MUL_EN               => FAST_MUL_EN,               -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN             => FAST_SHIFT_EN              -- use barrel shifter for shift operations
+    FAST_MUL_EN                => FAST_MUL_EN,                -- use DSPs for M extension's multiplier
+    FAST_SHIFT_EN              => FAST_SHIFT_EN               -- use barrel shifter for shift operations
   )
   port map (
     -- global control --

rtl/core/neorv32_cpu_alu.vhd

@@ -43,16 +43,17 @@ use neorv32.neorv32_package.all;
 
 entity neorv32_cpu_alu is
   generic (
-    XLEN                      : natural; -- data path width
+    XLEN                       : natural; -- data path width
     -- RISC-V CPU Extensions --
-    CPU_EXTENSION_RISCV_B     : boolean; -- implement bit-manipulation extension?
-    CPU_EXTENSION_RISCV_M     : boolean; -- implement mul/div extension?
-    CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
-    CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
-    CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
+    CPU_EXTENSION_RISCV_B      : boolean; -- implement bit-manipulation extension?
+    CPU_EXTENSION_RISCV_M      : boolean; -- implement mul/div extension?
+    CPU_EXTENSION_RISCV_Zmmul  : boolean; -- implement multiply-only M sub-extension?
+    CPU_EXTENSION_RISCV_Zfinx  : boolean; -- implement 32-bit floating-point extension (using INT reg!)
+    CPU_EXTENSION_RISCV_Zxcfu  : boolean; -- implement custom (instr.) functions unit?
+    CPU_EXTENSION_RISCV_Zicond : boolean; -- implement conditional operations extension?
     -- Extension Options --
-    FAST_MUL_EN               : boolean; -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN             : boolean  -- use barrel shifter for shift operations
+    FAST_MUL_EN                : boolean; -- use DSPs for M extension's multiplier
+    FAST_SHIFT_EN              : boolean  -- use barrel shifter for shift operations
   );
   port (
     -- global control --
@@ -364,10 +365,33 @@ begin
   end generate;
 
 
-  -- Co-Processor 5: Reserved ---------------------------------------------------------------
+  -- Co-Processor 5: Conditional Operations ('Zicond' Extension) ----------------------------
   -- -------------------------------------------------------------------------------------------
-  cp_result(5) <= (others => '0');
-  cp_valid(5)  <= '0';
+  neorv32_cpu_cp_cond_inst_true:
+  if (CPU_EXTENSION_RISCV_Zicond = true) generate
+    neorv32_cpu_cp_cond_inst: neorv32_cpu_cp_cond
+    generic map (
+      XLEN => XLEN -- data path width
+    )
+    port map (
+      -- global control --
+      clk_i   => clk_i,        -- global clock, rising edge
+      ctrl_i  => ctrl_i,       -- main control bus
+      start_i => cp_start(5),  -- trigger operation
+      -- data input --
+      rs1_i   => rs1_i,        -- rf source 1
+      rs2_i   => rs2_i,        -- rf source 2
+      -- result and status --
+      res_o   => cp_result(5), -- operation result
+      valid_o => cp_valid(5)
+    );
+  end generate;
+
+  neorv32_cpu_cp_cond_inst_false:
+  if (CPU_EXTENSION_RISCV_Zicond = false) generate
+    cp_result(5) <= (others => '0');
+    cp_valid(5)  <= '0';
+  end generate;
 
 
 end neorv32_cpu_cpu_rtl;