Vivado synthesis and loop limit for IMEM as ROM #1002
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I am hitting the following error when running a synthesis containing a large IMEM as ROM:
Since I only found one discussion mentioning this briefly in this repo I am making this discussion for future people with the same error. This is what my compiled program produced in sizes:
This is what I have my Vivado IP Block set to: And this is the bigger log produced by Vivado synthesis:
I am running out of BRAM blocks and Vivado is switching to registers maybe? Lets calculate. My Genesys2 for which I am synthesising has 16Mbits of BRAM available, so that is about
I believe this is also what is happening to my case. I suppose I will see if I can make my BRAM IP block a bit smaller. I can also maybe try from here to increase the loop limit but that will just increase the time Vivado will take to crash I am afraid. |
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Replies: 1 comment 6 replies
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I made my BRAM IP block smaller. Now it uses only 192 BRAM 36K blocks. That should leave Yet, synthesis failed again with the same error, so this change was not the solution I hoped it would be. I can try increasing the loop limit as well now and see if that helps. I should also note that the block design passes the I also noticed these warnings in my synthesis log file:
I am on commit |
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#1005 hopefully solves this issue.