How to build toochain with RISCV_B support?

[agamez]

I'm not able to build https://github.com/riscv-collab/riscv-gnu-toolchain.git like this:

./configure --prefix=/opt/riscv-b-bin --with-arch=rv32i_Zbs --with-abi=ilp32

I've also tried --with-arch=rv32i_zbs, --with-arch=rv32izbs, --with-arch=rv32ib and I don't remember what else. The error is not always the same, but it's clearly due to a mistake writing this. I also tried _Zba and _Zbb with no success.

Am i doing something wrong, or is this toolchain not supporting any of the B sub-extensions?

[stnolting]

The B ISA extension is already supported by upstream GCC - but I think it requires to specify the "sub-extensions" instead of just B as this has not been actually specified yet.

One of the latest toolchain I have build already support bit-manipulation instructions: https://github.com/stnolting/riscv-gcc-prebuilt/releases/tag/rv32i-4.0.0. This toolchain was configured as rv32i only (!), so all the pre-compiled / builtin libraries only used the base ISA. Anyway, it happily emits bit-manipulation instructions when properly invoked:

RV32IMCUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs

(from https://github.com/stnolting/neorv32-riscof/blob/ac347f7077a867f1557d4ae8e423a7088de3f05b/plugin-neorv32/neorv32_isa.yaml#L4)

[agamez]

I see... but I would expect this particular module, neorv32_gpio, to emit at least some of the related instructions, yet it's not happening

$ riscv32-unknown-elf-gcc -march=rv32i_zicsr -S neorv32_gpio.c -I../include -o /tmp/without.s
$ riscv32-unknown-elf-gcc -march=rv32i_zicsr_zba_zbb_zbc_zbs -S neorv32_gpio.c -I../include -o /tmp/with.s
$ diff -urN /tmp/with.s  /tmp/without.s 
--- /tmp/with.s	2023-03-23 07:42:20.763870487 +0100
+++ /tmp/without.s	2023-03-23 07:42:04.647962687 +0100
@@ -1,6 +1,6 @@
 	.file	"neorv32_gpio.c"
 	.option nopic
-	.attribute arch, "rv32i2p0_zba1p0_zbb1p0_zbc1p0_zbs1p0"
+	.attribute arch, "rv32i2p0"
 	.attribute unaligned_access, 0
 	.attribute stack_align, 16
 	.text

Or... maybe the code itself is not prone to generate bit manipulation instructions? Pin setting function for example should be a candidate for bseti

void neorv32_gpio_pin_set(int pin) {

  uint32_t mask = (uint32_t)(1 << (pin & 0x1f));

  if (pin < 32) {
    NEORV32_GPIO->OUTPUT_LO |= mask;
  }
  else {
    NEORV32_GPIO->OUTPUT_HI |= mask;
  }
}

[stnolting]

I see... but I would expect this particular module, neorv32_gpio, to emit at least some of the related instructions, yet it's not happening

Hmm, good point...

I just did a quick test.

C-code snippet:

  uint32_t data  = NEORV32_GPIO->OUTPUT_LO;
  uint32_t index = NEORV32_GPIO->INPUT_LO;
  data = data | (1 << (index & 0x1f));
  NEORV32_GPIO->OUTPUT_LO = data;

Compilation:

$ make UMARCH=rv32izicsr_zba_zbb_zbc_zbs EFFORT=-O2 clean_all exe asm

Generated assembly:

  uint32_t data  = NEORV32_GPIO->OUTPUT_LO;
     214:	fc802783          	lw	a5,-56(zero) # ffffffc8 <__crt0_stack_begin+0x7fffdfcc>
  uint32_t index = NEORV32_GPIO->INPUT_LO;
     218:	fc002703          	lw	a4,-64(zero) # ffffffc0 <__crt0_stack_begin+0x7fffdfc4>
  data = data | (1 << (index & 0x1f));
     21c:	28e797b3          	bset	a5,a5,a4
  NEORV32_GPIO->OUTPUT_LO = data;
     220:	fcf02423          	sw	a5,-56(zero) # ffffffc8 <__crt0_stack_begin+0x7fffdfcc>

The compiler emits a bset isntruction here. So in general this seems to work just fine.

[agamez]

Oh, now I see the difference. It's due to the -O2. It seems that -Os also generates bset instruction, so it seems everything's fine, just that some optimizations are needed for gcc to recognize the pattern. Thanks!