neorv32 setup for a digilent cmod-a7-35t board

[biosbob]

having exhausted the capacity of my icebreaker board, the cmod-a7-35t looks like a reasonable step up....

using /neorv32_setups/vivado/arty-a7-test-setup as my starting point, this project uses a "top-module" found in neorv32/rtl/test_setups....

having my own "top-module" which i've been using with icebreaker, i'm adapting this module to target the cmod-a7-35t....

question: is there an equivalent to the modules found in neorv32_setups/osflow/devices/ice40??? the neorv32/rtl/test_setups seem generic, as they lack device-specific memory or PLL support....

[biosbob]

for now, i'll follow the steps outlined in chapter 13 of the user's guide....

[stnolting]

using /neorv32_setups/vivado/arty-a7-test-setup as my starting point, this project uses a "top-module" found in neorv32/rtl/test_setups....

This file might be a little bit outdated - so use with caution 🙈

question: is there an equivalent to the modules found in neorv32_setups/osflow/devices/ice40??? the neorv32/rtl/test_setups seem generic, as they lack device-specific memory or PLL support....

No, there are not. The NEORV32 is written in a platform/technology/vendor agnostic style. The default memory modules from core/rtl/mem should infer block RAM for most target FPGAs (tested with Xilinx, Intel and Lattice).

PLLs and stuff like that are very platform-specific, so those cannot be inferred automatically. If you require a different clock than the one provided by your FPGA board, then you need to add this manually to your design.

[biosbob]

an update -- and some further questions....

my near-term goal is to re-use my "top-level" VHDL module within vivado.... initially, this module would be directly connected to the 12MHz clock on the CMOD board.... after that, i would use the vivado "clock wizard" to generate a 100MHz clock to drive the design....

with neorv32_em_cmod as my top module, i was able to successfully synthesize and run on my CMOD board.... once again, the signal clk_i was directly connected to the 12MHz clock on the board within my constraints.xdc file....

referring back to the diagram, i took the following steps to create a 100MHz clock:

• configured the clock-wizard element with a 12 MHz input (which it "knew" from my CMOD) and a 100MHz output
• renamed the external pins from the clock-wizard to clk_i and rstn_i (so i won't have to change my constraints.xdc file
• ran synthesis/implementation/generation as before
• adjusted the .bin file loaded onto the CMOD SPI flash (which worked just fine in my 12MHz baseline)

after loading the 100MHz bitstream and doing a power-on-reset, the same bootloader code used in my working 12MHz baseline fails to execute correctly.... if all were going well, i'd see a few bytes coming out the UART and a few GPIOs toggling....

my first question is about the relationship between the create_clock command and the clocking-wizard used in my block design.... right now, constraints.xdc contains the following:

set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { clk_i }];
##create_clock -add -name sys_clk -period 10.00 -waveform {0 5} [get_ports { clk_i }];

do i even need the create_clock command (commented out here), since the clocking-wizard element of my block design has the same information (and more!!!)????

notice that the clk_i port is presumably referring to the external pin within the block design; should i be more explicit and use a different name for this pin (say, sys_clk)????

were i to use the create_clock command, don't need to connect sys_clk (not clk_in) to something on my CMOD board????

does create_clock actually do what the name suggests, and perhaps i do not need to use the clocking wizard at all????

confession: this is really my time doing anything like this; and the documentation around vivado is quite confusing!!!!!

bottom line -- the CMOD is an attractive FPGA target, with significantly more LUTs than my iceBreaker.... all i want to do now is run at a faster speed than 12MHz 😉

[vhdlnerd]

If the 12MHz and 100Mhz clocks are the only clocks in the system, then the TIMING-6 warning should not be causing it not to work, in this case. Although, finding the source of the warning still should be done.
I need to see the timing report to know more. Can you put report (or better, the whole project zipped) in Dropbox or the like so I can access it?
I would not have time to look at it until after work (I'm in the US, Arizona).

[biosbob]

here's a link to a work.zip file containing the state of my project.... note that this project directory does not contain actual .vhd source files.... but for sure, you'll find all the timing reports....

[vhdlnerd]

I see this in the timing report:

Clock                               Waveform(ns)         Period(ns)      Frequency(MHz)
-----                               ------------         ----------      --------------
sys_clk                             {0.000 41.666}       83.333          12.000          
  clk_out1_em_design_clk_wiz_0_0_1  {0.000 5.000}        10.000          100.000         
  clkfbout_em_design_clk_wiz_0_0_1  {0.000 41.666}       83.333          12.000          
sys_clk_i                           {0.000 41.666}       83.333          12.000          
  clk_out1_em_design_clk_wiz_0_0    {0.000 5.000}        10.000          100.000         
  clkfbout_em_design_clk_wiz_0_0    {0.000 41.666}       83.333          12.000          

It looks like the clock constraints are being defined twice. However you created this project in Vivado, it created all the clock constrains you need. Try commenting out:
create_clock -add -name sys_clk -period 83.33 [get_ports { sys_clk_i }];
in your .xdc file, rebuild and see if there is only one set of clocks in the table (and hopefully, the warnings go away).

However, this does not explain why it is not working because it did meet timing at 100MHz.

The reset is tied to pin A18 which is button BTN0 on your board. But, the Cmod A7 Ref Manual shows this:

This means BTN0 would act like a active high reset not active low. Does it work if you hold down BTN0? (Of course, it means it should have worked how you had it originally.)

[biosbob]

i found the problem -- and it was on my end.... having said that, @vhdlnerd provided the key insight....

as i said originally, i was able to directly connect the 12MHz clock to neorv32_em_cmod.clk_i and had everything working just.... but (as @vhdlnerd pointed out above) BTN0 is actually active-high.... in fact, the neorv32_em_cmod.rstn_i input really is active high; i made the adjustment internally and should have renamed the symbol for clarity....

but when an "active-high reset" is driven by the locked output from the clocking wizard, we're inverted from what we should be!!!!!

i've quickly verified that everything IS working at 24MHz (taking a baby step).... i'll put some pieces together, clean-up the logic, and see how fast i can actually go....

we should be able to close out this discussion shortly....

[vhdlnerd]

I'm glad you got it to work!

[biosbob]

here's my cleaned-up block-design:

i was able to implement this design at 120MHz -- though i'll stick with 100MHz for now, as i will be adding more IP going forward.... and while this design exceeds the capacity of my iceBREAKER board, the CMOD-A7 has plenty of capacity here:

an interesting alternative dev board which is still <$100 -- but you do have to commit yourself to the vivado tools, which are anything but "lean-and-mean"....

i've also tried synthesizing this design for OrangeCrab -- nice, because i can use Yosys.... plenty of LUTs on this board, though max clock-speed is probably in the ~72MHz range....

[stnolting]

@biosbob

Great that your setup works now and thanks for sharing your FPGA results!
I'm curious - what kind of processor configuration do you use (enabled ISA extensions and peripherals, memory sizes)?

@vhdlnerd

Thank you very much for your excellent help here! 👍

[biosbob]

here's neorv32_em_cmod.vhd, which serves as my top-level module:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library neorv32;
use neorv32.neorv32_package.all;

entity neorv32_em_cmod is
    port (
        -- Clock and Reset --
        clk_i       : in  std_ulogic; -- global clock, rising edge
        rstn_i      : in  std_ulogic; -- global reset, low-active, async
        -- GPIO (available if IO_GPIO_EN = true) --
        gpio_o        : out std_ulogic_vector(6 downto 0); -- parallel output
       -- primary UART0 (available if IO_UART0_EN = true) --
        uart0_txd_o   : out std_logic; -- UART0 send data
        uart0_rxd_i   : in  std_logic  -- UART0 receive data
    );
end entity;

architecture neorv32_em_cmod_rtl of neorv32_em_cmod is

    signal gpio_o_int : std_ulogic_vector(63 downto 0);

begin

  -- The Core Of The Problem ----------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  neorv32_top_inst: neorv32_top
    generic map (
        -- General --
        CLOCK_FREQUENCY              => 100000000,          -- clock frequency of clk_i in Hz
        INT_BOOTLOADER_EN            => true,               -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
        -- RISC-V CPU Extensions --
        CPU_EXTENSION_RISCV_C        => true,               -- implement compressed extension?
        CPU_EXTENSION_RISCV_M        => true,               -- implement mul/div extension?
        CPU_EXTENSION_RISCV_U        => true,               -- implement user mode extension?
        CPU_EXTENSION_RISCV_Zicntr   => true,               -- implement base counters?
        CPU_EXTENSION_RISCV_Zifencei => true,               -- implement instruction stream sync.?
        -- Tuning Options --
        FAST_MUL_EN                  => true,               -- use DSPs for M extension's multiplier
        FAST_SHIFT_EN                => true,               -- use barrel shifter for shift operations
        CPU_IPB_ENTRIES              => 2,                  -- entries in instruction prefetch buffer, has to be a power of 2, min 1
        -- Internal Instruction memory --
        MEM_INT_IMEM_EN              => true,               -- implement processor-internal instruction memory
        MEM_INT_IMEM_SIZE            => 8*1024,             -- size of processor-internal instruction memory in bytes
        -- Internal Data memory --
        MEM_INT_DMEM_EN              => true,               -- implement processor-internal data memory
        MEM_INT_DMEM_SIZE            => 8*1024,             -- size of processor-internal data memory in bytes
        -- External Interrupts Controller (XIRQ) --
        XIRQ_NUM_CH                  => 1,                  -- number of external IRQ channels (0..32)
        XIRQ_TRIGGER_TYPE            => x"ffffffff",        -- trigger type: 0=level, 1=edge
        XIRQ_TRIGGER_POLARITY        => x"ffffffff",        -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
        -- Processor peripherals --
        IO_DMA_EN                    => true,               -- implement direct memory access controller (DMA)?        
        IO_GPIO_NUM                  => 8,                  -- number of GPIO input/output pairs (0..64)
        IO_GPTMR_EN                  => true,               -- implement general purpose timer (GPTMR)?
--        IO_MTIME_EN                  => true,               -- implement machine system timer (MTIME)?
        IO_UART0_EN                  => true,               -- implement primary universal asynchronous receiver/transmitter (UART0)?
        IO_XIP_EN                    => true                -- implement execute in place module (XIP)?
    )
    port map (
        -- Global control --
        clk_i       => clk_i,           -- global clock, rising edge
        rstn_i      => rstn_i,          -- global reset, low-active, async
        -- GPIO (available if IO_GPIO_NUM > 0) --
        gpio_o      => gpio_o_int,      -- parallel output
        -- primary UART0 (available if IO_UART0_EN = true) --
        uart0_txd_o => uart0_txd_o,     -- UART0 send data
        uart0_rxd_i => uart0_rxd_i      -- UART0 receive data
    );

    gpio_o <= gpio_o_int(6 downto 0);

end architecture;

not all that much here -- but this design already exceeded the capacity of my iceBREAKER board....

[stnolting]

Thanks! 👍