Problem with my data send from C application to wishbone bus

[50L31L]

HI @stnolting,
I've made in C on the neorv32 an application that send data that are contains in a tab[], to my wishbone bus and i want to get them.
Here is the code :

const uint32_t tab[] = {
0xf00f00f0,0x0f00f00f,0x00f00f00,
};

and in my main i got :

int main() {
         ////////////////////////////////////////
        //////////////// SETUP  ////////////////
        ////////////////////////////////////////

    
    neorv32_rte_setup();
    neorv32_uart0_setup(BAUD_RATE, 0);
    if (neorv32_gpio_available() == 0) {
        neorv32_uart0_puts("Error! No GPIO unit synthesized!\n");
        return 1; // nope, no GPIO unit synthesized
    }

    // check if XIRQ unit is implemented at all
    if (neorv32_xirq_available() == 0) {
        neorv32_uart0_printf("XIRQ not synthesized!\n");
        return 1;
    }

    // say hello
    neorv32_uart0_puts("Hello from Neorv32 and ZCU104 \n");

    while(1){
            neorv32_cpu_store_unsigned_word(0x00084000,background[0]);
            neorv32_cpu_store_unsigned_word(0x00084000,background[1]);
            neorv32_cpu_store_unsigned_word(0x00084000,background[2]);
        }

return 0;
}

then on the nex side on vivado after generating project on FPGA, I use an ILA to see my data in real time.
Sometimes some of the data are not send, for exemple i can have only 0x0f00f00f and 0x00f00f00 but not 0xf00f00f0 and it is important for my applicaton to hav the data in order.
here is a picture of my ILA and what i got :

[stnolting]

Hey @50L31L.

I assume background[] is tab[] here, right?

while(1){
  neorv32_cpu_store_unsigned_word(0x00084000,background[0]);
  neorv32_cpu_store_unsigned_word(0x00084000,background[1]);
  neorv32_cpu_store_unsigned_word(0x00084000,background[2]);
}

Sometimes some of the data are not send, for exemple i can have only 0x0f00f00f and 0x00f00f00 but not 0xf00f00f0 and it is important for my applicaton to hav the data in order.
here is a picture of my ILA and what i got :

Note that all Wishbone/XBUS signals are valid only if xbus_cyc_o is high (see https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus -> "Wishbone Protocol").

So there is no actual Wishbone transaction in your first image (at least not where your arrows are pointing).

The Wishbone/XBUS signals (except for xbus_cyc_o and xbus_stb_o) are changing all the time because they are driven by the processor-internal bus lines. For example, if the CPU is accessing the internal data memory, you will also see the according address and read/write data at the Wishbone/XBUS data ports.

You can add a "gating logic" that will prevent the Wishbone/XBUS lines from changing when there is no actual Wishbone/XBUS transaction. This option is enabled by setting XBUS_REGSTAGE_EN => true.

[50L31L]

what does your processor configuration looks like? Are you using any caches (i.e. d-cache and/or xbus-cache)?

I have not enabled any caches on the processor.

You are writing to address 0x00084000. By default, there is no processor-internal device mapped to this address. Hence, the request is forwarded to the XBUS interface. But what comes next? Just a single custom module or are you using an entire interconnect with several devices?

To explain here is my goal: display an image on a screen, I use a VGA connection. I then have in my table my pixels of the image. I send these pixels on the whishbone bus which is then transformed into AXI-Stream. Then I use IPs which generate me the RGB signals for the VGA.

Since you have enabled the RTE in your code (neorv32_rte_setup();) you should see some debug info in your UART console if the bus accesses to this address encounter an error. Do you see any output from the RTE?

Here is the C code that send the array:

while(1)
{
    for (int i = 0 ; i < end_of_background; i++)
    {
        neorv32_cpu_store_unsigned_word(0x00084000,background[i]);
        
    }
}   

background[] corresponds to my array
end_of_background = last value of my array
the address 0x00084000 is connected to the external bus here are the RTE errors that I get:

<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>
sprite send 
<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>
sprite send 
<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>
sprite send 
<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>
sprite send 
<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>
sprite send 
<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>

sprite send is printed when i got an interruption when the display is back to the top so each new image printed, the interruption code does this :

void xirq_handler_sprite_IRQ(void) {
    //neorv32_uart0_printf("sprite IRQ \n");

   
    for (i_sprite = 2 ; i_sprite < end_of_teemoo; i_sprite++)
    {
        *sprite_ptr = teemo[i_sprite];
       
    }
    neorv32_uart0_puts("sprite send \n");

    neorv32_xirq_clear_pending(4); // clear pending interrupt of channel 0
    neorv32_xirq_global_enable();
}

and the Sprite display is working, but not the background

but I can't figure out what's causing the problem.

Still thank you for all the help you are providing.

[stnolting]

I send these pixels on the whishbone bus which is then transformed into AXI-Stream.

Just as a hint: the NEORV32 provides a stream link interface (SLINK) that can emit AXI4-stream compatible stream data.

Here is the C code that send the array:

Your code looks just fine.

<NEORV32-RTE> [M] Store access fault @ PC=0x00000400, MTINST=0x00A5A023, MTVAL=0x00084000 </NEORV32-RTE>

That does not look good. The CPU encountered a bus exception while writing to address 0x00084000 (=MTVAL). Does this happen all the time? It seems like the accessed device (the module connected to the external bus interface) does not respond with an ACK - or it does not respond within a bound time window.

[50L31L]

Hello
I come with new things,
I've fixed the error related to rte.
But it's looks like my problem is related to the clock speed of the processor.
Currently my processor is using a clk_i of 100 MHz :

CLOCK_FREQUENCY              : natural := 100000000;      -- clock frequency of clk_i in Hz
clk_i       => clk_100_Mhz

I expected the processor to perform a write action every clock cycle, but it does it every 53 clock cycles. The images below show a counter that increments every 100 clock cycles and the difference between the two write actions is 53 (the last signal is the counter).

Is that normal ? or is there a way to make write action more faster ?

Thanks

[stnolting]

Is that normal ? or is there a way to make write action more faster ?

I depends on your application, but in general, yes, this is normal. 😉

Memory accesses consist not only of the actual LOAD/STORE operations, but also of instructions for pointer increments, loops, etc. The CPU therefore needs several clock cycles to execute a single memory access (e.g. writing a single word). If you need faster memory transfers without so much overhead, you could either optimize your code (for example using the Duff's Device approach) or you could use the processor's DMA.