How to create tri-state interface in block design?

[franksmicro]

I am having an issue creating a tristate output (specifically, for onewire) using the neorv32 wrapper in a Vivado block design.

Using logic as described in the Datasheet, I created a VHDL module (relevant lines shown below):

entity tristate is
    Port ( bus_o : in STD_LOGIC;
           bus_i : out STD_LOGIC;
           bus_io : inout STD_LOGIC);
end tristate;

architecture Behavioral of tristate is

begin
    bus_io <= '0' when (bus_o = '0') else 'Z'; -- drive
    bus_i <= std_ulogic(bus_io); -- sense
end Behavioral;

I then right-click in the diagram and select Add Module. I connect the bus_i pin to onewire_i on the neorv32, and the bus_o pin to the onewire_o pin. I then attempt to connect bus_io to a board pin referenced in the constraint file.

I have tried both "Make External" and "Create Port" on the bus_io pin. In either case, I get the following error when implementing the design:

[Designutils 20-1595] In entity design_1_tristate_0_0, connectivity of net bus_io cannot be represented in VHDL. VHDL lacks syntax to connect the following inout terminals to a differently-named net: 
   inout bus_io

Resolution: Check whether terminals really need inout direction and substitute input or output as needed. It may also be possible to rename the net to match the terminal.

I'm guessing I probably am taking the wrong approach here, but I'm not sure how this should be done. I have successfully used onewire in a non-block design where I instantiate a neorv32 instance from Verilog using similar logic to that above with the io wire being and inout port in the top design.

[stnolting]

Hey @franksmicro!

I am having an issue creating a tristate output (specifically, for onewire) using the neorv32 wrapper in a Vivado block design.

Oh I know what you're talking about! 😅 Vivado has some issues inferring tri-state drivers that are not at the top level...

Using logic as described in the Datasheet, I created a VHDL module (relevant lines shown below):

So you wrap-up this logic as another IP block for the block design? Sounds right, but also very complicated?! 🤔

For block designs I just use the "Utility Buffer" from the IP catalogue and configure it as simple IOBUF:

Here is the documentation: https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/IOBUF
But be careful - the output-enable is low-active.

Just add two of them and connect them right to the core's TWI ports. Use a single "Constant" block with "Value = 0" to tie the output signal to low (I don't know why I am using two of them here...) and make the "IO" ports external. To be precise, these tri-state drivers are not at the top level either... However, Vivado is happy with this. 😉

[franksmicro]

Thanks for the quick response!

For some reason, my version of Vivado (2023.2) does not have IOBUF available as a choice for Utility Buffer. However, I noticed that IOBUF is available from HDL. So I wrote an HDL module that simply passes through the IOBUF lines, and added it as a module to my diagram. I then connected it up as shown in the above diagram. I can confirm that my onewire design now works!

In case anyone else runs into IOBUF not being available in their version of Utility Buffer, I am including my code (it is in Verilog, but the same could be done with VHDL) below. To use, add a new RTL file to the project, then right-click on the diagram and select Add Module. Connect as shown above.

`default_nettype none

module iobuf(
    input wire I,
    input wire T,
    output wire O,
    inout wire IO
);

   // IOBUF: Single-ended Bi-directional Buffer
   //        All devices
   // Xilinx HDL Language Template, version 2023.2

   IOBUF #(
      .DRIVE(12), // Specify the output drive strength
      .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
      .IOSTANDARD("DEFAULT"), // Specify the I/O standard
      .SLEW("SLOW") // Specify the output slew rate
   ) IOBUF_inst (
      .O(O),     // Buffer output
      .IO(IO),   // Buffer inout port (connect directly to top-level port)
      .I(I),     // Buffer input
      .T(T)      // 3-state enable input, high=input, low=output
   );

   // End of IOBUF_inst instantiation

endmodule

[stnolting]

For some reason, my version of Vivado (2023.2) does not have IOBUF available as a choice for Utility Buffer.

Oh, what? I mean it is a basic IO primitive... maybe the name just changed?!

So I wrote an HDL module that simply passes through the IOBUF lines, and added it as a module to my diagram. I then connected it up as shown in the above diagram. I can confirm that my onewire design now works!

Nice workaround! 👍

[franksmicro]

It literally does not show up as an option for Utility Buffer in Vivado 2023.2.1: