Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[rtl] fix some Verilog [sic] issues #1103

Merged
merged 4 commits into from
Nov 26, 2024
Merged

[rtl] fix some Verilog [sic] issues #1103

merged 4 commits into from
Nov 26, 2024

Conversation

stnolting
Copy link
Owner

Fix some HDL issues that caused problem when converting the code to RTL (https://github.com/stnolting/neorv32-verilog). Identified by @pluseqs in #1100.

  • cache: fix missing type conversion
  • dma: config seems to be a reserved word in Verilog

@stnolting stnolting added the HW Hardware-related label Nov 26, 2024
@stnolting stnolting self-assigned this Nov 26, 2024
@stnolting stnolting marked this pull request as ready for review November 26, 2024 19:09
@stnolting stnolting merged commit 3fe0b11 into main Nov 26, 2024
2 checks passed
@stnolting stnolting deleted the verilog_fixes branch November 26, 2024 19:21
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
HW Hardware-related
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant