RISC-V "Zicntr" and "Zihpm" extensions

[stnolting]

This PR adds two new configuration generics to the processor top entity:

  CPU_EXTENSION_RISCV_Zicntr : boolean := true;   -- implement base counters?
  CPU_EXTENSION_RISCV_Zihpm  : boolean := false;  -- implement hardware performance monitors?

These new generics are used to explicitly control implementation of the Zicntr and Zihpm ISA extensions. Both extensions can still be customized using the CPU_CNT_WIDTH (actually physical size of CPU counters) and HPM_NUM_CNTS (acatual physical number of HPM counters) generics.

Rationale: "Define the Zicntr and Zihpm extensions" - https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20211029-4e4dfff

Zicntr - Basic CPU counters ISA extension

In order to implement the CPU base counters (which is required by the RISC-V spec), the CPU_EXTENSION_RISCV_Zicntr generic has to be enabled.

Affected CSRs:

• time[h] System time - low/high word (from MTIME)
• [m]cycle[h] Cycle counter - low/high word
• [m]instret[h] Retired instructions counter - low/high word

The SYSINFO flag SYSINFO_CPU_ZXNOCNT (no counters implemented) has been replaced by the SYSINFO_CPU_ZICNTR flag, which now indicates that the counters are implemented (inversion). Furthermore, this flag now also includes the time[h] CSRs.

Zihpm - Hardware performance monitors ISA extension

In order to implement the hardware performance monitors, the CPU_EXTENSION_RISCV_Zihpm generic has to be enabled.

Affected CSRs:

• mhpmevent3 ... mhpmevent31 HMP event configuration CSRs
• mhpmcounter3[h] ... mhpmcounter31[h] HPM counters - low/high word

The SYSINFO flag SYSINFO_CPU_HPM has been renamed to SYSINFO_CPU_ZIHPM.

⚠️ Note that all of the NEORV32 HPM CSRs are accessible in machine-mode only.

Backwards-Compatibility

✔️ CPU_EXTENSION_RISCV_Zicntr is true per default - base counters are implemented by default.
❌ CPU_EXTENSION_RISCV_Zihpm has to be set true to implement the HPM CSRs.

[umarcor]

Shall we update https://github.com/stnolting/neorv32/blob/master/sim/run_riscv_arch_test.sh#L50-L60 accordingly? I.e., are there specific test suites for these extensions?

[stnolting]

Hey!

Zicnt is part of the "basic" privilege architecture (like Zicsr) and is always expected to be available.

There are no tests in the RISC-V arch-test setup for the Zihpm extension as most of the features are entirely platform-specific (like the events that trigger a certain hardware performance monitor to increment).