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[rtl] cleanup top's generics #557

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Mar 18, 2023
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[rtl] cleanup top's generics #557

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014d293
[rtl] CFS: change conduit size generics to type natural
stnolting Mar 18, 2023
4e290eb
[rtl] generics cleanup
stnolting Mar 18, 2023
c89f5f0
[rtl/processor_templates] generic cleanups
stnolting Mar 18, 2023
4c65442
[rtl/system_integration] generic cleanups
stnolting Mar 18, 2023
177e782
[sim] update top generics
stnolting Mar 18, 2023
962e1f6
[CHANGELOG] add v1.8.2.6
stnolting Mar 18, 2023
785b954
[docs] update mvendorid and hartid CSRs
stnolting Mar 18, 2023
5c578a2
[rtl/processor_templates] remove HART_ID assignment
stnolting Mar 18, 2023
269cf00
[JTAG tap] hardwire identifier to all-zero
stnolting Mar 18, 2023
0b02801
[docs] update generics list
stnolting Mar 18, 2023
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -31,6 +31,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12

| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 18.03.2023 | 1.8.2.6 | add new generic `JEDEC_ID` (official JEDEC identifier; used for the `mvendorid`); further generics cleanups; [#557](https://github.com/stnolting/neorv32/pull/557)
| 17.03.2023 | 1.8.2.5 | add RISC-V `time[h]` CSRs (part of the `Zicntr` ISA extension); [#556](https://github.com/stnolting/neorv32/pull/556) |
| 17.03.2023 | 1.8.2.4 | re-add VHDL process names; [#555](https://github.com/stnolting/neorv32/pull/555) |
| 15.03.2023 | 1.8.2.3 | rtl reworks, cleanups and optimizations; [#550](https://github.com/stnolting/neorv32/pull/550) |
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8 changes: 4 additions & 4 deletions docs/datasheet/cpu_csr.adoc
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Expand Up @@ -82,7 +82,7 @@ should always read back a CSR after writing to check if the targeted bits can ac
| 0xF11 | <<_mvendorid>> | `CSR_MVENDORID` | r/- | Machine vendor ID
| 0xF12 | <<_marchid>> | `CSR_MARCHID` | r/- | Machine architecture ID
| 0xF13 | <<_mimpid>> | `CSR_MIMPID` | r/- | Machine implementation ID / version
| 0xF14 | <<_mhartid>> | `CSR_MHARTID` | r/- | Machine thread ID
| 0xF14 | <<_mhartid>> | `CSR_MHARTID` | r/- | Machine hardware thread ID
| 0xF15 | <<_mconfigptr>> | `CSR_MCONFIGPTR` | r/- | Machine configuration pointer register
5+^| **<<_neorv32_specific_csrs>>**
| 0xFC0 | <<_mxisa>> | `CSR_MXISA` | r/- | NEORV32-specific "extended" machine CPU ISA and extensions
Expand Down Expand Up @@ -785,9 +785,9 @@ counter CSRs are read-only. Any write access will raise an illegal instruction e
|=======================
| Name | Machine vendor ID
| Address | `0xf11`
| Reset value | `0x00000000`
| Reset value | `DEFINED`
| ISA | `Zicsr`
| Description | The features of this CSR are not implemented yet. The register is read-only and always returns zero.
| Description | Vendor ID (JEDEC identifier), assigned via the `VENDOR_ID` top generic (<<_processor_top_entity_generics>>).
|=======================


Expand Down Expand Up @@ -835,7 +835,7 @@ NEORV32 as BCD-coded number (example: `mimpid` = _0x01020312_ → 01.02.03.12
| Reset value | `DEFINED`
| ISA | `Zicsr`
| Description | The `mhartid` CSR is read-only and provides the core's hart ID,
which is assigned via the `HW_THREAD_ID` top generic.
which is assigned via the `HW_THREAD_ID` top generic (<<_processor_top_entity_generics>>).
|=======================


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2 changes: 1 addition & 1 deletion docs/datasheet/on_chip_debugger.adoc
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Expand Up @@ -107,7 +107,7 @@ register. The following table shows the available data registers and their addre
[options="header",grid="rows"]
|=======================
| Address (via `IR`) | Name | Size [bits] | Description
| `00001` | `IDCODE` | 32 | identifier, default: `0x0CAFE001` (configurable via package's `jtag_tap_idcode_*` constants)
| `00001` | `IDCODE` | 32 | identifier, hardwired to `0x00000001`
| `10000` | `DTMCS` | 32 | debug transport module control and status register
| `10001` | `DMI` | 40 | debug module interface (_dmi_); 6-bit address, 32-bit read/write data, 2-bit operation (`00` = NOP; `10` = write; `01` = read)
| others | `BYPASS` | 1 | default JTAG bypass register
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9 changes: 5 additions & 4 deletions docs/datasheet/soc.adoc
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Expand Up @@ -191,8 +191,9 @@ The generic type "suv(x:y)" defines a `std_ulogic_vector(x downto y)`.
4+^| **General**
| `CLOCK_FREQUENCY` | natural | - | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
| `INT_BOOTLOADER_EN` | boolean | false | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image.
| `HW_THREAD_ID` | natural | 0 | The hart ID of the CPU.
| `CUSTOM_ID` | suv(31:0) | 0x00000000 | User-defined identifier to identify a certain setup or to pass user-defined flags to software.
| `HART_ID` | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSRs).
| `VENDOR_ID` | suv(31:0) | 0x00000000 | JEDEC ID (passed to <<_mvendorid>> CSRs).
| `CUSTOM_ID` | suv(31:0) | 0x00000000 | User-defined identifier to identify a certain setup or to pass user-defined flags to software (via the <<_system_configuration_information_memory_sysinfo>>).
| `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger <<_on_chip_debugger_ocd>> and the CPU debug mode.
4+^| **CPU <<_instruction_sets_and_extensions>>**
| `CPU_EXTENSION_RISCV_B` | boolean | false | Enable <<_b_isa_extension>> (bit-manipulation).
Expand Down Expand Up @@ -260,8 +261,8 @@ The generic type "suv(x:y)" defines a `std_ulogic_vector(x downto y)`.
| `IO_TRNG_FIFO` | natural | 1 | Depth of the TRNG data FIFO. Has to be a power of two, min 1, max 32768.
| `IO_CFS_EN` | boolean | false | Implement the <<_custom_functions_subsystem_cfs>>.
| `IO_CFS_CONFIG` | suv(31:0) | 0x00000000 | "Conduit" generic to pass user-defined flags to the <<_custom_functions_subsystem_cfs>>.
| `IO_CFS_IN_SIZE` | positive | 32 | Size of the <<_custom_functions_subsystem_cfs>> input signal conduit (`cfs_in_i`).
| `IO_CFS_OUT_SIZE` | positive | 32 | Size of the <<_custom_functions_subsystem_cfs>> output signal conduit (`cfs_out_o`).
| `IO_CFS_IN_SIZE` | natural | 32 | Size of the <<_custom_functions_subsystem_cfs>> input signal conduit (`cfs_in_i`).
| `IO_CFS_OUT_SIZE` | natural | 32 | Size of the <<_custom_functions_subsystem_cfs>> output signal conduit (`cfs_out_o`).
| `IO_NEOLED_EN` | boolean | false | Implement the <<_smart_led_interface_neoled>>.
| `IO_NEOLED_TX_FIFO` | natural | 1 | TX FIFO depth of the the <<_smart_led_interface_neoled>>. Has to be a power of two, min 1, max 32768.
| `IO_GPTMR_EN` | boolean | false | Implement the <<_general_purpose_timer_gptmr>>.
Expand Down
2 changes: 1 addition & 1 deletion docs/userguide/debugging_with_ocd.adoc
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Expand Up @@ -74,7 +74,7 @@ libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : clock speed 1000 kHz
Info : JTAG tap: neorv32.cpu tap/device found: 0x0cafe001 (mfg: 0x000 (<invalid>), part: 0xcafe, ver: 0x0)
Info : JTAG tap: neorv32.cpu tap/device found: 0x00000000 (mfg: 0x000 (<invalid>), part: 0x0000, ver: 0x0)
Info : datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
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4 changes: 2 additions & 2 deletions rtl/core/neorv32_cfs.vhd
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Expand Up @@ -49,8 +49,8 @@ use neorv32.neorv32_package.all;
entity neorv32_cfs is
generic (
CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
CFS_IN_SIZE : positive; -- size of CFS input conduit in bits
CFS_OUT_SIZE : positive -- size of CFS output conduit in bits
CFS_IN_SIZE : natural; -- size of CFS input conduit in bits
CFS_OUT_SIZE : natural -- size of CFS output conduit in bits
);
port (
-- host access --
Expand Down
6 changes: 4 additions & 2 deletions rtl/core/neorv32_cpu.vhd
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Expand Up @@ -42,7 +42,8 @@ use neorv32.neorv32_package.all;
entity neorv32_cpu is
generic (
-- General --
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
HART_ID : std_ulogic_vector(31 downto 0); -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
CPU_DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
Expand Down Expand Up @@ -260,7 +261,8 @@ begin
generic map (
-- General --
XLEN => XLEN, -- data path width
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
HART_ID => HART_ID, -- hardware thread ID
VENDOR_ID => VENDOR_ID, -- vendor's JEDEC ID
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
CPU_DEBUG_PARK_ADDR => CPU_DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR => CPU_DEBUG_EXC_ADDR, -- cpu debug mode exception entry address
Expand Down
15 changes: 8 additions & 7 deletions rtl/core/neorv32_cpu_control.vhd
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Expand Up @@ -53,7 +53,8 @@ entity neorv32_cpu_control is
generic (
-- General --
XLEN : natural; -- data path width
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
HART_ID : std_ulogic_vector(31 downto 0); -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
CPU_DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
Expand Down Expand Up @@ -138,7 +139,7 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH-32, 0));

-- instruction fetch engine --
type fetch_engine_state_t is (IF_RESTART, IF_REQUEST, IF_PENDING, IF_WAIT); -- better use one-hot encoding
type fetch_engine_state_t is (IF_RESTART, IF_REQUEST, IF_PENDING, IF_WAIT);
type fetch_engine_t is record
state : fetch_engine_state_t;
state_prev : fetch_engine_state_t;
Expand Down Expand Up @@ -2310,10 +2311,10 @@ begin

-- machine information registers --
-- --------------------------------------------------------------------
-- when csr_mvendorid_c => csr.rdata <= (others => '0'); -- vendor ID, implemented but always zero
when csr_mvendorid_c => csr.rdata <= VENDOR_ID; -- vendor'S JEDEC ID
when csr_marchid_c => csr.rdata(4 downto 0) <= "10011"; -- architecture ID - official RISC-V open-source arch ID
when csr_mimpid_c => csr.rdata <= hw_version_c; -- implementation ID -- NEORV32 hardware version
when csr_mhartid_c => csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32)); -- hardware thread ID
when csr_mhartid_c => csr.rdata <= HART_ID; -- hardware thread ID
-- when csr_mconfigptr_c => csr.rdata <= (others => '0'); -- machine configuration pointer register, implemented but always zero

-- debug mode CSRs --
Expand All @@ -2338,14 +2339,14 @@ begin
-- machine extended ISA extensions information --
when csr_mxisa_c =>
-- extended ISA (sub-)extensions --
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr: privileged architecture (!!!)
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr: CSR access
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei: instruction stream sync.
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div
csr.rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicond); -- Zicond: conditional operations
csr.rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers, "F-alternative"
csr.rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers
-- csr.rdata(06) <= '0'; -- reserved
csr.rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base instructions, cycle and time CSRs
csr.rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base counters
csr.rdata(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP: physical memory protection (Zspmp)
csr.rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors
csr.rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Sdext); -- Sdext: RISC-V (external) debug mode
Expand Down
24 changes: 11 additions & 13 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -58,14 +58,9 @@ package neorv32_package is
-- log2 of co-processor timeout cycles --
constant cp_timeout_c : natural := 7; -- default = 7 (= 128 cycles)

-- JTAG tap - identifier --
constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id

-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080205"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080206"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID

-- Check if we're inside the Matrix -------------------------------------------------------
Expand Down Expand Up @@ -972,7 +967,8 @@ package neorv32_package is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- vendor's JEDEC ID
CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
Expand Down Expand Up @@ -1043,8 +1039,8 @@ package neorv32_package is
IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
IO_CFS_IN_SIZE : natural := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : natural := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED FIFO depth, has to be a power of two, min 1
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
Expand Down Expand Up @@ -1132,7 +1128,8 @@ package neorv32_package is
component neorv32_cpu
generic (
-- General --
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
HART_ID : std_ulogic_vector(31 downto 0); -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
CPU_DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
Expand Down Expand Up @@ -1205,7 +1202,8 @@ package neorv32_package is
generic (
-- General --
XLEN : natural; -- data path width
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
HART_ID : std_ulogic_vector(31 downto 0); -- hardware thread ID
VENDOR_ID : std_ulogic_vector(31 downto 0); -- vendor's JEDEC ID
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
CPU_DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address
CPU_DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address
Expand Down Expand Up @@ -1956,8 +1954,8 @@ package neorv32_package is
component neorv32_cfs
generic (
CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
CFS_IN_SIZE : positive; -- size of CFS input conduit in bits
CFS_OUT_SIZE : positive -- size of CFS output conduit in bits
CFS_IN_SIZE : natural; -- size of CFS input conduit in bits
CFS_OUT_SIZE : natural -- size of CFS output conduit in bits
);
port (
-- host access --
Expand Down
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